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| author | Arturs Artamonovs <arturs.artamonovs@protonmail.com> | 2024-11-03 15:56:55 +0000 |
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| committer | Arturs Artamonovs <arturs.artamonovs@protonmail.com> | 2024-11-03 15:56:55 +0000 |
| commit | cf4444e7390365df43ecbd3d130015c1e06ef88f (patch) | |
| tree | 8a6eb114135a04d5efd5af213577b4fac47532ae /Radio/HW/BladeRF/src/board/bladerf1/compatibility.c | |
| parent | ca50c0f64f1b2fce46b4cb83ed111854bac13852 (diff) | |
| download | PrySDR-cf4444e7390365df43ecbd3d130015c1e06ef88f.tar.gz PrySDR-cf4444e7390365df43ecbd3d130015c1e06ef88f.zip | |
BladeRF library compiles
Diffstat (limited to 'Radio/HW/BladeRF/src/board/bladerf1/compatibility.c')
| -rw-r--r-- | Radio/HW/BladeRF/src/board/bladerf1/compatibility.c | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/Radio/HW/BladeRF/src/board/bladerf1/compatibility.c b/Radio/HW/BladeRF/src/board/bladerf1/compatibility.c new file mode 100644 index 0000000..6d76d3f --- /dev/null +++ b/Radio/HW/BladeRF/src/board/bladerf1/compatibility.c @@ -0,0 +1,75 @@ +#include "host_config.h" + +#include "helpers/version.h" + +/* Firmware-FPGA compatibility tables + * + * This list should be kept in decending order, such that the most recent + * versions are first, and the last entry should contain the earliest version + * that libbladeRF supports. + */ + +#define VERSION(major, minor, patch) { major, minor, patch, NULL } + +static const struct compat fw_compat[] = { + /* Firmware requires >= FPGA */ + { VERSION(2, 4, 0), VERSION(0, 6, 0) }, + { VERSION(2, 3, 2), VERSION(0, 0, 2) }, + { VERSION(2, 3, 1), VERSION(0, 0, 2) }, + { VERSION(2, 3, 0), VERSION(0, 0, 2) }, + { VERSION(2, 2, 0), VERSION(0, 0, 2) }, + { VERSION(2, 1, 1), VERSION(0, 0, 2) }, + { VERSION(2, 1, 0), VERSION(0, 0, 2) }, + { VERSION(2, 0, 0), VERSION(0, 0, 2) }, + { VERSION(1, 9, 1), VERSION(0, 0, 2) }, + { VERSION(1, 9, 0), VERSION(0, 0, 2) }, + { VERSION(1, 8, 1), VERSION(0, 0, 2) }, + { VERSION(1, 8, 0), VERSION(0, 0, 2) }, + { VERSION(1, 7, 1), VERSION(0, 0, 2) }, + { VERSION(1, 7, 0), VERSION(0, 0, 2) }, + { VERSION(1, 6, 1), VERSION(0, 0, 2) }, + { VERSION(1, 6, 0), VERSION(0, 0, 1) }, +}; + +const struct version_compat_table bladerf1_fw_compat_table = {fw_compat, ARRAY_SIZE(fw_compat)}; + +static const struct compat fpga_compat[] = { + /* FPGA requires >= Firmware */ + { VERSION(0, 15, 1), VERSION(2, 4, 0) }, + { VERSION(0, 15, 0), VERSION(2, 4, 0) }, + { VERSION(0, 14, 0), VERSION(2, 4, 0) }, + { VERSION(0, 12, 0), VERSION(2, 2, 0) }, + { VERSION(0, 11, 1), VERSION(2, 1, 0) }, + { VERSION(0, 11, 0), VERSION(1, 6, 1) }, + { VERSION(0, 10, 2), VERSION(1, 6, 1) }, + { VERSION(0, 10, 1), VERSION(1, 6, 1) }, + { VERSION(0, 10, 0), VERSION(1, 6, 1) }, + { VERSION(0, 9, 0), VERSION(1, 6, 1) }, + { VERSION(0, 8, 0), VERSION(1, 6, 1) }, + { VERSION(0, 7, 3), VERSION(1, 6, 1) }, + { VERSION(0, 7, 2), VERSION(1, 6, 1) }, + { VERSION(0, 7, 1), VERSION(1, 6, 1) }, + { VERSION(0, 7, 0), VERSION(1, 6, 1) }, + { VERSION(0, 6, 0), VERSION(1, 6, 1) }, + { VERSION(0, 5, 0), VERSION(1, 6, 1) }, + { VERSION(0, 4, 1), VERSION(1, 6, 1) }, + { VERSION(0, 4, 0), VERSION(1, 6, 1) }, + { VERSION(0, 3, 5), VERSION(1, 6, 1) }, + { VERSION(0, 3, 4), VERSION(1, 6, 1) }, + { VERSION(0, 3, 3), VERSION(1, 6, 1) }, + { VERSION(0, 3, 2), VERSION(1, 6, 1) }, + { VERSION(0, 3, 1), VERSION(1, 6, 1) }, + { VERSION(0, 3, 0), VERSION(1, 6, 1) }, + { VERSION(0, 2, 0), VERSION(1, 6, 1) }, + { VERSION(0, 1, 2), VERSION(1, 6, 1) }, + { VERSION(0, 1, 1), VERSION(1, 6, 1) }, + { VERSION(0, 1, 0), VERSION(1, 6, 1) }, + { VERSION(0, 0, 6), VERSION(1, 6, 1) }, + { VERSION(0, 0, 5), VERSION(1, 6, 1) }, + { VERSION(0, 0, 4), VERSION(1, 6, 1) }, + { VERSION(0, 0, 3), VERSION(1, 6, 1) }, + { VERSION(0, 0, 2), VERSION(1, 6, 1) }, + { VERSION(0, 0, 1), VERSION(1, 6, 0) }, +}; + +const struct version_compat_table bladerf1_fpga_compat_table = {fpga_compat, ARRAY_SIZE(fpga_compat)}; |