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-rw-r--r--cpu8/cpu_reg/Makefile12
-rw-r--r--cpu8/cpu_reg/cpu_reg.cpp96
-rw-r--r--cpu8/cpu_reg/cpu_reg.hpp61
3 files changed, 169 insertions, 0 deletions
diff --git a/cpu8/cpu_reg/Makefile b/cpu8/cpu_reg/Makefile
new file mode 100644
index 0000000..c37accb
--- /dev/null
+++ b/cpu8/cpu_reg/Makefile
@@ -0,0 +1,12 @@
+SYSTEMC_PATH=/home/fam/downloads/source/systemc/systemc-2.3.2
+SYSTEMC_INC=$(SYSTEMC_PATH)/src
+SYSTEMC_LIB=$(SYSTEMC_PATH)/src/.libs
+
+PROJECT=cpu_reg
+
+make:
+ g++ $(PROJECT).cpp -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB) -Wl,-rpath=$(SYSTEMC_LIB)\
+ -o $(PROJECT) -lsystemc -lm
+
+
+
diff --git a/cpu8/cpu_reg/cpu_reg.cpp b/cpu8/cpu_reg/cpu_reg.cpp
new file mode 100644
index 0000000..17f4a72
--- /dev/null
+++ b/cpu8/cpu_reg/cpu_reg.cpp
@@ -0,0 +1,96 @@
+#include <iostream>
+#include <iomanip>
+
+#include "systemc.h"
+#include "systemc"
+#include <sysc/tracing/sc_trace.h>
+#include <sysc/tracing/sc_vcd_trace.h>
+
+#include "cpu_reg.hpp"
+
+SC_MODULE(test_cpu_reg)
+{
+ sc_out<bool> d,e;
+ sc_in<bool> clk;
+
+ void test_cpu_reg_stim()
+ {
+ wait();
+ d.write(0);
+ e.write(0);
+
+ wait();
+ d.write(1);
+ e.write(0);
+
+ wait();
+ d.write(0);
+ e.write(1);
+
+ wait();
+ d.write(1);
+ e.write(1);
+
+ wait();
+ d.write(0);
+ e.write(0);
+
+ wait();
+ d.write(1);
+ e.write(0);
+
+ wait();
+ d.write(0);
+ e.write(1);
+
+ wait();
+ d.write(0);
+ e.write(0);
+
+
+ wait();
+
+ sc_stop();
+ }
+
+ SC_CTOR(test_cpu_reg)
+ {
+ SC_THREAD(test_cpu_reg_stim);
+ sensitive << clk.pos();
+
+ }
+};
+
+
+int sc_main(int argc, char **argv) {
+ int i;
+ sc_signal<bool> sig_in_d,sig_in_e, sig_out_q, sig_out_nq;
+ sc_clock TestClk("TestClk", 10, SC_NS, 0.5, 1, SC_NS);
+
+ test_cpu_reg Stim1("Stimulus");
+ Stim1.e(sig_in_e);
+ Stim1.d(sig_in_d);
+ Stim1.clk(TestClk);
+
+
+
+ cpu_reg DUT("cpu_reg");
+ DUT.in_d(sig_in_d);
+ DUT.in_e(sig_in_e);
+ DUT.out_q(sig_out_q);
+ DUT.out_nq(sig_out_nq);
+
+
+ sc_trace_file *Tf;
+
+ Tf = sc_create_vcd_trace_file("trace_cpu_reg.dat");
+ sc_trace(Tf, sig_in_d, "D");
+ sc_trace(Tf, sig_in_e, "E");
+ sc_trace(Tf, sig_out_q, "Q");
+ sc_trace(Tf, sig_out_nq, "NQ");
+
+ sc_start();
+ sc_close_vcd_trace_file(Tf);
+
+ return(0);
+} \ No newline at end of file
diff --git a/cpu8/cpu_reg/cpu_reg.hpp b/cpu8/cpu_reg/cpu_reg.hpp
new file mode 100644
index 0000000..15e2a3e
--- /dev/null
+++ b/cpu8/cpu_reg/cpu_reg.hpp
@@ -0,0 +1,61 @@
+#ifndef __SYSC_CPU_REG_HPP
+#define __SYSC_CPU_REG_HPP
+
+#include "systemc.h"
+#include "../cpu_and/cpu_and.hpp"
+#include "../cpu_not/cpu_not.hpp"
+#include "../cpu_srlatch/cpu_srlatch.hpp"
+
+SC_MODULE (cpu_reg)
+{
+ //Inputs
+ sc_in <bool> in_d;
+ sc_in <bool> in_e;
+ sc_in <bool> in_r;
+ sc_out <bool> out_q,out_nq;
+
+ cpu_and *and1, *and2;
+ cpu_not *not1;
+ cpu_srlatch *srlatch1;
+
+ sc_signal<bool> sig_not1and1;
+ sc_signal<bool> sig_and1srlatch1;
+ sc_signal<bool> sig_and2srlatch1;
+
+ void do_reg()
+ {
+
+ }
+
+ SC_CTOR(cpu_reg)
+ {
+
+ and1 = new cpu_and("AND1");
+ and2 = new cpu_and("AND2");
+ not1 = new cpu_not("NOT1");
+ srlatch1 = new cpu_srlatch("SRLATCH1");
+
+
+ and1->in_a(sig_not1and1);
+ and1->in_b(in_e);
+ and1->out_c(sig_and1srlatch1);
+
+ and2->in_a(in_d);
+ and2->in_b(in_e);
+ and2->out_c(sig_and2srlatch1);
+
+ not1->in_a(in_d);
+ not1->out_b(sig_not1and1);
+
+ srlatch1->in_r(sig_and1srlatch1);
+ srlatch1->in_s(sig_and2srlatch1);
+ srlatch1->out_q(out_q);
+ srlatch1->out_nq(out_nq);
+
+ //SC_METHOD(do_reg);
+ //sensitive << in_d << in_clk;
+ }
+
+};
+
+#endif \ No newline at end of file