From 3e1eb700dd4fc8dc47772ff7942990e61dcde32e Mon Sep 17 00:00:00 2001
From: FreeArtMan <dos21h@gmail.com>
Date: Tue, 4 Dec 2018 21:22:39 +0000
Subject: Different versions of register d-flip-flop, sr-latch, all have
 issues, becouse of no delay, and cpu_code_reg implemented without gate logic

---
 cpu8/cpu_code_reg/Makefile         | 12 ++++++
 cpu8/cpu_code_reg/cpu_code_reg.cpp | 82 ++++++++++++++++++++++++++++++++++++++
 cpu8/cpu_code_reg/cpu_code_reg.hpp | 39 ++++++++++++++++++
 3 files changed, 133 insertions(+)
 create mode 100644 cpu8/cpu_code_reg/Makefile
 create mode 100644 cpu8/cpu_code_reg/cpu_code_reg.cpp
 create mode 100644 cpu8/cpu_code_reg/cpu_code_reg.hpp

(limited to 'cpu8/cpu_code_reg')

diff --git a/cpu8/cpu_code_reg/Makefile b/cpu8/cpu_code_reg/Makefile
new file mode 100644
index 0000000..e8c3514
--- /dev/null
+++ b/cpu8/cpu_code_reg/Makefile
@@ -0,0 +1,12 @@
+SYSTEMC_PATH=/home/fam/downloads/source/systemc/systemc-2.3.2
+SYSTEMC_INC=$(SYSTEMC_PATH)/src
+SYSTEMC_LIB=$(SYSTEMC_PATH)/src/.libs
+
+PROJECT=cpu_code_reg
+
+make:
+	g++ $(PROJECT).cpp -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB) -Wl,-rpath=$(SYSTEMC_LIB)\
+		-o $(PROJECT) -lsystemc -lm
+
+
+
diff --git a/cpu8/cpu_code_reg/cpu_code_reg.cpp b/cpu8/cpu_code_reg/cpu_code_reg.cpp
new file mode 100644
index 0000000..d312cd7
--- /dev/null
+++ b/cpu8/cpu_code_reg/cpu_code_reg.cpp
@@ -0,0 +1,82 @@
+#include <iostream>
+#include <iomanip>
+
+#include "systemc.h"
+#include "systemc"
+#include <sysc/tracing/sc_trace.h>
+#include <sysc/tracing/sc_vcd_trace.h>
+
+#include "cpu_code_reg.hpp"
+
+SC_MODULE(test_cpu_code_reg)
+{
+	sc_out<bool> d,e;
+	sc_in<bool> clk;
+
+	void test_cpu_reg_stim()
+	{
+		wait();
+		d.write(0);
+		e.write(0);
+
+		wait();
+		d.write(1);
+		e.write(0);
+
+		wait();
+		d.write(0);
+		e.write(1);
+
+		wait();
+		d.write(1);
+		e.write(1);
+
+		wait();
+		d.write(0);
+		e.write(0);
+
+		wait();
+		d.write(1);
+		e.write(0);
+
+		wait();
+
+		sc_stop();
+	}
+
+	SC_CTOR(test_cpu_code_reg)
+	{
+		SC_THREAD(test_cpu_reg_stim);
+		sensitive << clk.pos();
+
+	}
+};
+
+
+int sc_main(int argc, char **argv) {
+	int i;
+	sc_signal<bool> sig_in_d,sig_in_e, sig_out_q;
+	sc_clock TestClk("TestClk", 10, SC_NS, 0.5, 1, SC_NS);
+
+	test_cpu_code_reg Stim1("Stimulus");
+	Stim1.e(sig_in_e);
+	Stim1.d(sig_in_d);
+	Stim1.clk(TestClk);
+
+	cpu_code_reg DUT("cpu_code_eg");
+	DUT.in_d(sig_in_d);
+	DUT.in_e(sig_in_e);
+	DUT.out_q(sig_out_q);
+
+	sc_trace_file *Tf;
+	
+	Tf = sc_create_vcd_trace_file("trace_cpu_code_reg.dat");
+	sc_trace(Tf, sig_in_d, "D");
+	sc_trace(Tf, sig_in_e, "E");
+	sc_trace(Tf, sig_out_q, "Q");
+
+	sc_start();
+	sc_close_vcd_trace_file(Tf);
+
+	return(0);
+}
\ No newline at end of file
diff --git a/cpu8/cpu_code_reg/cpu_code_reg.hpp b/cpu8/cpu_code_reg/cpu_code_reg.hpp
new file mode 100644
index 0000000..c48a256
--- /dev/null
+++ b/cpu8/cpu_code_reg/cpu_code_reg.hpp
@@ -0,0 +1,39 @@
+#ifndef __SYSC_CPU_CODE_REG_HPP
+#define __SYSC_CPU_CODE_REG_HPP
+
+#include "systemc.h"
+#include "../cpu_and/cpu_and.hpp"
+#include "../cpu_not/cpu_not.hpp"
+#include "../cpu_srlatch/cpu_srlatch.hpp"
+
+SC_MODULE (cpu_code_reg) 
+{
+	//Inputs
+	sc_port<sc_signal_in_if<bool>,0> in_d;
+	sc_port<sc_signal_in_if<bool>,0> in_e;
+	//Outputs
+	sc_port<sc_signal_out_if<bool>,0> out_q;
+	//Internal variables
+	bool bit=false;
+
+	void do_code_reg()
+	{
+		//if enabled
+		if (in_e[0]->read())
+		{
+			//set data
+			bit = in_d[0]->read();
+		}
+		//no delay
+		out_q[0]->write(bit);
+	}
+
+	SC_CTOR(cpu_code_reg)
+	{	
+		SC_METHOD(do_code_reg);
+		sensitive << in_d << in_e;
+	}
+
+};
+
+#endif
\ No newline at end of file
-- 
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