From 3e1eb700dd4fc8dc47772ff7942990e61dcde32e Mon Sep 17 00:00:00 2001
From: FreeArtMan <dos21h@gmail.com>
Date: Tue, 4 Dec 2018 21:22:39 +0000
Subject: Different versions of register d-flip-flop, sr-latch, all have
 issues, becouse of no delay, and cpu_code_reg implemented without gate logic

---
 cpu8/cpu_nand/cpu_nand.hpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'cpu8/cpu_nand')

diff --git a/cpu8/cpu_nand/cpu_nand.hpp b/cpu8/cpu_nand/cpu_nand.hpp
index 5e5e517..8194998 100644
--- a/cpu8/cpu_nand/cpu_nand.hpp
+++ b/cpu8/cpu_nand/cpu_nand.hpp
@@ -5,13 +5,13 @@
 
 SC_MODULE (cpu_nand) 
 {
-	sc_in <bool> in_a;
-	sc_in <bool> in_b;
-	sc_out <bool> out_c;
+	sc_port<sc_signal_in_if<bool>,0> in_a;
+	sc_port<sc_signal_in_if<bool>,0> in_b;
+	sc_port<sc_signal_out_if<bool>,0> out_c;
 
 	void do_nand()
 	{
-		out_c.write( !(in_a.read() && in_b.read()) );
+		out_c[0]->write( !(in_a[0]->read() && in_b[0]->read()) );
 	}
 
 	SC_CTOR(cpu_nand)
-- 
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