From 7e00e4960af68e6c26104cca26cdf47f4f4095a7 Mon Sep 17 00:00:00 2001 From: FreeArtMan Date: Mon, 3 Dec 2018 00:28:25 +0000 Subject: Added initial CPU SR-latch --- cpu8/cpu_srlatch/cpu_srlatch.cpp | 98 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 cpu8/cpu_srlatch/cpu_srlatch.cpp (limited to 'cpu8/cpu_srlatch/cpu_srlatch.cpp') diff --git a/cpu8/cpu_srlatch/cpu_srlatch.cpp b/cpu8/cpu_srlatch/cpu_srlatch.cpp new file mode 100644 index 0000000..07efe5e --- /dev/null +++ b/cpu8/cpu_srlatch/cpu_srlatch.cpp @@ -0,0 +1,98 @@ +#include +#include + +#include "systemc.h" +#include "systemc" +#include +#include + +#include "cpu_srlatch.hpp" + +SC_MODULE(test_cpu_srlatch) +{ + sc_out s,r; + sc_in clk; + + + void test_cpu_srlatch_stim() + { + wait(); + s.write(0); + r.write(1); + + wait(); + s.write(1); + r.write(0); + + wait(); + s.write(1); + r.write(1); + + wait(); + s.write(1); + r.write(0); + + wait(); + s.write(0); + r.write(0); + + + wait(); + s.write(0); + r.write(0); + + wait(); + s.write(0); + r.write(1); + + wait(); + s.write(0); + r.write(0); + + wait(); + s.write(0); + r.write(0); + + + wait(); + + sc_stop(); + } + + SC_CTOR(test_cpu_srlatch) + { + SC_THREAD(test_cpu_srlatch_stim); + sensitive << clk.pos(); + + } +}; + + +int sc_main(int argc, char **argv) { + sc_signal sig_in_r, sig_in_s, sig_out_q, sig_out_nq; + sc_clock TestClk("TestClk", 10, SC_NS, 0.5, 1, SC_NS); + + test_cpu_srlatch Stim1("Stimulus"); + Stim1.r(sig_in_r); + Stim1.s(sig_in_s); + Stim1.clk(TestClk); + + cpu_srlatch DUT("cpu_srlatch"); + DUT.in_r(sig_in_r); + DUT.in_s(sig_in_s); + DUT.out_q(sig_out_q); + DUT.out_nq(sig_out_nq); + + sc_trace_file *Tf; + + Tf = sc_create_vcd_trace_file("trace_cpu_srlatch.dat"); + sc_trace(Tf, sig_in_r, "IN_R"); + sc_trace(Tf, sig_in_s, "IN_S"); + sc_trace(Tf, sig_out_q, "OUT_Q"); + sc_trace(Tf, sig_out_nq, "OUT_NQ"); + + sc_start(); + sc_close_vcd_trace_file(Tf); + + return(0); +} \ No newline at end of file -- cgit v1.2.3