| Branch | Commit message | Author | Age | |
|---|---|---|---|---|
| master | Add alu v0.1_16bit. compiles without warning risc cpu | dianshi | 2 years | |
| Age | Commit message | Author | Files | Lines |
| 2022-02-14 | Add alu v0.1_16bit. compiles without warning risc cpuHEADmaster | dianshi | 3 | -0/+119 |
| 2022-02-14 | Add running risc 16bit cpu v0.1 | dianshi | 3 | -20/+36 |
| 2022-02-14 | Add datapatch v0.1 | dianshi | 6 | -0/+401 |
| 2022-02-13 | Add control unit version 0.1 | dianshi | 3 | -0/+224 |
| 2022-01-25 | Add alu_control version v0.1 | dianshi | 3 | -0/+109 |
| 2022-01-19 | Added general purpose memory | dianshi | 3 | -0/+134 |
| 2022-01-19 | Add instruction memory | dianshi | 5 | -0/+88 |
| 2022-01-13 | Added datamem with 8bytes of memory | dianshi | 4 | -0/+146 |
| 2022-01-05 | Update AND model | dianshi | 1 | -9/+3 |
| 2022-01-05 | Added ALU | dianshi | 3 | -0/+130 |
| [...] | ||||
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index : cpu8_v.git | |
| 8bit cpu implementation in verilog | dianshi |
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