| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add alu v0.1_16bit. compiles without warning risc cpuHEADmaster | dianshi | 2022-02-14 | 3 | -0/+119 |
| * | Add running risc 16bit cpu v0.1 | dianshi | 2022-02-14 | 3 | -20/+36 |
| * | Add datapatch v0.1 | dianshi | 2022-02-14 | 6 | -0/+401 |
| * | Add control unit version 0.1 | dianshi | 2022-02-13 | 3 | -0/+224 |
| * | Add alu_control version v0.1 | dianshi | 2022-01-25 | 3 | -0/+109 |
| * | Added general purpose memory | dianshi | 2022-01-19 | 3 | -0/+134 |
| * | Add instruction memory | dianshi | 2022-01-19 | 5 | -0/+88 |
| * | Added datamem with 8bytes of memory | dianshi | 2022-01-13 | 4 | -0/+146 |
| * | Update AND model | dianshi | 2022-01-05 | 1 | -9/+3 |
| * | Added ALU | dianshi | 2022-01-05 | 3 | -0/+130 |
| * | Added and8 | dianshi | 2022-01-05 | 5 | -0/+131 |
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index : cpu8_v.git | |
| 8bit cpu implementation in verilog | dianshi |
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