From 87d81f71cb794bbaf653098bfd88d0f59d7b20d5 Mon Sep 17 00:00:00 2001
From: dianshi <dianshi@main.lv>
Date: Wed, 5 Jan 2022 20:54:13 +0000
Subject: Added and8

---
 and/v0.1/testbench.v | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 and/v0.1/testbench.v

(limited to 'and/v0.1/testbench.v')

diff --git a/and/v0.1/testbench.v b/and/v0.1/testbench.v
new file mode 100644
index 0000000..1832e60
--- /dev/null
+++ b/and/v0.1/testbench.v
@@ -0,0 +1,49 @@
+`timescale 1ns/1ps
+
+module testbench;
+
+reg data_1=0;
+reg data_2=0;
+//reg [7:0]data2;
+
+wire  val;
+wire  out;
+//wire  [7:0]out2;
+
+//assign val=data;
+and1 uut (
+    .a(data_1),
+    .b(data_2),
+    .c(out)
+);
+/*
+and8 uut1 (
+    .a(data2),
+    .b(out2)
+);*/
+
+initial begin
+    $dumpfile("test_and.vcd");
+    $dumpvars(0,testbench);
+    data_1=0;
+    data_2=0;
+    #1 data_1=1;
+    data_2=0;
+
+    #10 data_1=0;
+    data_2=1;
+
+    #20 data_1=1;
+    data_2=1;
+
+    #30 data_1=0;
+    data_2=0;
+
+    #40;
+end
+
+initial begin
+    $monitor("At time %t d1=%h(%0d) d2=%h(%0d) ",$time,data_1,data_1,data_2,data_2);
+end 
+
+endmodule
\ No newline at end of file
-- 
cgit v1.2.3