From 2a54718dc842d1be84d1470827b538bdaab2cb28 Mon Sep 17 00:00:00 2001 From: dianshi Date: Sun, 13 Feb 2022 21:34:02 +0000 Subject: Add control unit version 0.1 --- control_unit/v0.1/control_unit.v | 195 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 195 insertions(+) create mode 100644 control_unit/v0.1/control_unit.v (limited to 'control_unit/v0.1/control_unit.v') diff --git a/control_unit/v0.1/control_unit.v b/control_unit/v0.1/control_unit.v new file mode 100644 index 0000000..2fdfc14 --- /dev/null +++ b/control_unit/v0.1/control_unit.v @@ -0,0 +1,195 @@ +module control_unit( + input [3:0] opcode, + output reg[1:0] alu_op, + output reg jump, bne, beq, mem_read, mem_write, alu_src, reg_dst, mem_to_reg, reg_write +); + +always @(*) +begin + case(opcode) + 4'b0000: // LW + begin + reg_dst = 1'b0; + alu_src = 1'b1; + mem_to_reg = 1'b1; + reg_write = 1'b1; + mem_read = 1'b1; + mem_write = 1'b0; + beq = 1'b0; + bne = 1'b0; + alu_op = 2'b10; + jump = 1'b0; + end + 4'b0001: // SW + begin + reg_dst = 1'b0; + alu_src = 1'b1; + mem_to_reg = 1'b0; + reg_write = 1'b0; + mem_read = 1'b0; + mem_write = 1'b1; + beq = 1'b0; + bne = 1'b0; + alu_op = 2'b10; + jump = 1'b0; + end + 4'b0010: // data_processing + begin + reg_dst = 1'b1; + alu_src = 1'b0; + mem_to_reg = 1'b0; + reg_write = 1'b1; + mem_read = 1'b0; + mem_write = 1'b0; + beq = 1'b0; + bne = 1'b0; + alu_op = 2'b00; + jump = 1'b0; + end + 4'b0011: // data_processing + begin + reg_dst = 1'b1; + alu_src = 1'b0; + mem_to_reg = 1'b0; + reg_write = 1'b1; + mem_read = 1'b0; + mem_write = 1'b0; + beq = 1'b0; + bne = 1'b0; + alu_op = 2'b00; + jump = 1'b0; + end + 4'b0100: // data_processing + begin + reg_dst = 1'b1; + alu_src = 1'b0; + mem_to_reg = 1'b0; + reg_write = 1'b1; + mem_read = 1'b0; + mem_write = 1'b0; + beq = 1'b0; + bne = 1'b0; + alu_op = 2'b00; + jump = 1'b0; + end + 4'b0101: // data_processing + begin + reg_dst = 1'b1; + alu_src = 1'b0; + mem_to_reg = 1'b0; + reg_write = 1'b1; + mem_read = 1'b0; + mem_write = 1'b0; + beq = 1'b0; + bne = 1'b0; + alu_op = 2'b00; + jump = 1'b0; + end + 4'b0110: // data_processing + begin + reg_dst = 1'b1; + alu_src = 1'b0; + mem_to_reg = 1'b0; + reg_write = 1'b1; + mem_read = 1'b0; + mem_write = 1'b0; + beq = 1'b0; + bne = 1'b0; + alu_op = 2'b00; + jump = 1'b0; + end + 4'b0111: // data_processing + begin + reg_dst = 1'b1; + alu_src = 1'b0; + mem_to_reg = 1'b0; + reg_write = 1'b1; + mem_read = 1'b0; + mem_write = 1'b0; + beq = 1'b0; + bne = 1'b0; + alu_op = 2'b00; + jump = 1'b0; + end + 4'b1000: // data_processing + begin + reg_dst = 1'b1; + alu_src = 1'b0; + mem_to_reg = 1'b0; + reg_write = 1'b1; + mem_read = 1'b0; + mem_write = 1'b0; + beq = 1'b0; + bne = 1'b0; + alu_op = 2'b00; + jump = 1'b0; + end + 4'b1001: // data_processing + begin + reg_dst = 1'b1; + alu_src = 1'b0; + mem_to_reg = 1'b0; + reg_write = 1'b1; + mem_read = 1'b0; + mem_write = 1'b0; + beq = 1'b0; + bne = 1'b0; + alu_op = 2'b00; + jump = 1'b0; + end + + 4'b1011: // BEQ + begin + reg_dst = 1'b0; + alu_src = 1'b0; + mem_to_reg = 1'b0; + reg_write = 1'b0; + mem_read = 1'b0; + mem_write = 1'b0; + beq = 1'b1; + bne = 1'b0; + alu_op = 2'b01; + jump = 1'b0; + end + 4'b1100: // BNE + begin + reg_dst = 1'b0; + alu_src = 1'b0; + mem_to_reg = 1'b0; + reg_write = 1'b0; + mem_read = 1'b0; + mem_write = 1'b0; + beq = 1'b0; + bne = 1'b1; + alu_op = 2'b01; + jump = 1'b0; + end + 4'b1101: // J + begin + reg_dst = 1'b0; + alu_src = 1'b0; + mem_to_reg = 1'b0; + reg_write = 1'b0; + mem_read = 1'b0; + mem_write = 1'b0; + beq = 1'b0; + bne = 1'b0; + alu_op = 2'b00; + jump = 1'b1; + end + default: begin + reg_dst = 1'b1; + alu_src = 1'b0; + mem_to_reg = 1'b0; + reg_write = 1'b1; + mem_read = 1'b0; + mem_write = 1'b0; + beq = 1'b0; + bne = 1'b0; + alu_op = 2'b00; + jump = 1'b0; + end + endcase +end + +endmodule \ No newline at end of file -- cgit v1.2.3