From f3a300ce5927cad9ecf02821b3be007f9d2af22b Mon Sep 17 00:00:00 2001 From: dianshi Date: Wed, 19 Jan 2022 22:00:08 +0000 Subject: Add instruction memory --- instrmem/v0.1/parameters.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 instrmem/v0.1/parameters.h (limited to 'instrmem/v0.1/parameters.h') diff --git a/instrmem/v0.1/parameters.h b/instrmem/v0.1/parameters.h new file mode 100644 index 0000000..4935dfc --- /dev/null +++ b/instrmem/v0.1/parameters.h @@ -0,0 +1,13 @@ +`ifndef PARAMETERS_H_ +`define PARAMETERS_H_ +// fpga4student.com +// FPGA projects, VHDL projects, Verilog projects +// Verilog code for RISC Processor +// Parameter file +`define col 16 // 16 bits instruction memory, data memory +`define row_i 15 // instruction memory, instructions number, this number can be changed. Adding more instructions to verify your design is a good idea. +`define row_d 8 // The number of data in data memory. We only use 8 data. Do not change this number. You can change the value of each data inside test.data file. Total number is fixed at 8. +`define filename "./test/50001111_50001212.o" +`define simulation_time #160 + +`endif \ No newline at end of file -- cgit v1.2.3