From f52f1af38851b784862175ff2806bda622b0ec47 Mon Sep 17 00:00:00 2001 From: dianshi Date: Mon, 14 Feb 2022 07:48:24 +0000 Subject: Add datapatch v0.1 --- risc_16bit_cpu/v0.1/Makefile | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 risc_16bit_cpu/v0.1/Makefile (limited to 'risc_16bit_cpu/v0.1/Makefile') diff --git a/risc_16bit_cpu/v0.1/Makefile b/risc_16bit_cpu/v0.1/Makefile new file mode 100644 index 0000000..5d6accc --- /dev/null +++ b/risc_16bit_cpu/v0.1/Makefile @@ -0,0 +1,26 @@ +make: + iverilog -g2005-sv -o alu_8 alu_8.v + iverilog -g2005-sv -o data_memory data_memory.v + iverilog -g2005-sv -o instr_memory instr_memory.v + iverilog -g2005-sv -o gpr_register gpr_register.v + iverilog -g2005-sv -o alu_control alu_control.v + iverilog -g2005-sv -o data_path data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v + iverilog -g2005-sv -o control_unit control_unit.v + iverilog -g2005-sv -o risc_16bit_cpu risc_16bit_cpu.v control_unit.v data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v + iverilog -g2005-sv -o test_data_memory data_memory.v test_data_memory.v + iverilog -g2005-sv -o test_instr_memory instr_memory.v test_instr_memory.v + iverilog -g2005-sv -o test_gpr_register gpr_register.v test_gpr_register.v + iverilog -g2005-sv -o test_alu_control alu_control.v test_alu_control.v + iverilog -g2005-sv -o test_data_path data_path.v test_data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v + iverilog -g2005-sv -o test_risc_16bit_cpu test_risc_16bit_cpu.v risc_16bit_cpu.v control_unit.v data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v + +test: + ./test_data_memory + ./test_instr_memory + ./test_gpr_register + ./test_alu_control + ./test_data_path + ./test_risc_16bit_cpu + +wave: + gtkwave test_data_path.vcd \ No newline at end of file -- cgit v1.2.3