From f52f1af38851b784862175ff2806bda622b0ec47 Mon Sep 17 00:00:00 2001 From: dianshi Date: Mon, 14 Feb 2022 07:48:24 +0000 Subject: Add datapatch v0.1 --- risc_16bit_cpu/v0.1/risc_16bit_cpu.v | 43 ++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 risc_16bit_cpu/v0.1/risc_16bit_cpu.v (limited to 'risc_16bit_cpu/v0.1/risc_16bit_cpu.v') diff --git a/risc_16bit_cpu/v0.1/risc_16bit_cpu.v b/risc_16bit_cpu/v0.1/risc_16bit_cpu.v new file mode 100644 index 0000000..8ad4b96 --- /dev/null +++ b/risc_16bit_cpu/v0.1/risc_16bit_cpu.v @@ -0,0 +1,43 @@ + +module risc_16bit_cpu( + input clk +); + + +wire jump,bne,beq,mem_read,mem_write,alu_src,reg_dst,mem_to_reg,reg_write; + wire[1:0] alu_op; + wire [3:0] opcode; + // Datapath + data_path DU + ( + .clk(clk), + .jump(jump), + .beq(beq), + .mem_read(mem_read), + .mem_write(mem_write), + .alu_src(alu_src), + .reg_dst(reg_dst), + .mem_to_reg(mem_to_reg), + .reg_write(reg_write), + .bne(bne), + .alu_op(alu_op), + .opcode(opcode) + ); + // control unit + control_unit control + ( + .opcode(opcode), + .reg_dst(reg_dst), + .mem_to_reg(mem_to_reg), + .alu_op(alu_op), + .jump(jump), + .bne(bne), + .beq(beq), + .mem_read(mem_read), + .mem_write(mem_write), + .alu_src(alu_src), + .reg_write(reg_write) + ); + + +endmodule \ No newline at end of file -- cgit v1.2.3