From f52f1af38851b784862175ff2806bda622b0ec47 Mon Sep 17 00:00:00 2001
From: dianshi <dianshi@main.lv>
Date: Mon, 14 Feb 2022 07:48:24 +0000
Subject: Add datapatch v0.1

---
 risc_16bit_cpu/v0.1/Makefile              | 26 +++++++++++++++++++
 risc_16bit_cpu/v0.1/risc_16bit_cpu.v      | 43 +++++++++++++++++++++++++++++++
 risc_16bit_cpu/v0.1/test_risc_16bit_cpu.v | 28 ++++++++++++++++++++
 3 files changed, 97 insertions(+)
 create mode 100644 risc_16bit_cpu/v0.1/Makefile
 create mode 100644 risc_16bit_cpu/v0.1/risc_16bit_cpu.v
 create mode 100644 risc_16bit_cpu/v0.1/test_risc_16bit_cpu.v

(limited to 'risc_16bit_cpu/v0.1')

diff --git a/risc_16bit_cpu/v0.1/Makefile b/risc_16bit_cpu/v0.1/Makefile
new file mode 100644
index 0000000..5d6accc
--- /dev/null
+++ b/risc_16bit_cpu/v0.1/Makefile
@@ -0,0 +1,26 @@
+make:
+	iverilog -g2005-sv -o alu_8 alu_8.v
+	iverilog -g2005-sv -o data_memory data_memory.v
+	iverilog -g2005-sv -o instr_memory instr_memory.v
+	iverilog -g2005-sv -o gpr_register gpr_register.v
+	iverilog -g2005-sv -o alu_control alu_control.v
+	iverilog -g2005-sv -o data_path data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v
+	iverilog -g2005-sv -o control_unit control_unit.v
+	iverilog -g2005-sv -o risc_16bit_cpu risc_16bit_cpu.v control_unit.v data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v
+	iverilog -g2005-sv -o test_data_memory data_memory.v test_data_memory.v
+	iverilog -g2005-sv -o test_instr_memory instr_memory.v test_instr_memory.v
+	iverilog -g2005-sv -o test_gpr_register gpr_register.v test_gpr_register.v
+	iverilog -g2005-sv -o test_alu_control alu_control.v test_alu_control.v
+	iverilog -g2005-sv -o test_data_path data_path.v test_data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v
+	iverilog -g2005-sv -o test_risc_16bit_cpu test_risc_16bit_cpu.v risc_16bit_cpu.v control_unit.v data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v
+
+test:
+	./test_data_memory
+	./test_instr_memory
+	./test_gpr_register
+	./test_alu_control
+	./test_data_path
+	./test_risc_16bit_cpu
+
+wave:
+	gtkwave test_data_path.vcd
\ No newline at end of file
diff --git a/risc_16bit_cpu/v0.1/risc_16bit_cpu.v b/risc_16bit_cpu/v0.1/risc_16bit_cpu.v
new file mode 100644
index 0000000..8ad4b96
--- /dev/null
+++ b/risc_16bit_cpu/v0.1/risc_16bit_cpu.v
@@ -0,0 +1,43 @@
+
+module risc_16bit_cpu(
+ input clk
+);
+
+
+wire jump,bne,beq,mem_read,mem_write,alu_src,reg_dst,mem_to_reg,reg_write;
+ wire[1:0] alu_op;
+ wire [3:0] opcode;
+ // Datapath
+ data_path DU
+ (
+  .clk(clk),
+  .jump(jump),
+  .beq(beq),
+  .mem_read(mem_read),
+  .mem_write(mem_write),
+  .alu_src(alu_src),
+  .reg_dst(reg_dst),
+  .mem_to_reg(mem_to_reg),
+  .reg_write(reg_write),
+  .bne(bne),
+  .alu_op(alu_op),
+  .opcode(opcode)
+ );
+ // control unit
+ control_unit control
+ (
+  .opcode(opcode),
+  .reg_dst(reg_dst),
+  .mem_to_reg(mem_to_reg),
+  .alu_op(alu_op),
+  .jump(jump),
+  .bne(bne),
+  .beq(beq),
+  .mem_read(mem_read),
+  .mem_write(mem_write),
+  .alu_src(alu_src),
+  .reg_write(reg_write)
+ );
+
+
+endmodule
\ No newline at end of file
diff --git a/risc_16bit_cpu/v0.1/test_risc_16bit_cpu.v b/risc_16bit_cpu/v0.1/test_risc_16bit_cpu.v
new file mode 100644
index 0000000..1853474
--- /dev/null
+++ b/risc_16bit_cpu/v0.1/test_risc_16bit_cpu.v
@@ -0,0 +1,28 @@
+`include "parameters.h"
+
+module test_risc_16bit_cpu;
+
+// Inputs
+reg clk;
+
+// Instantiate the Unit Under Test (UUT)
+risc_16bit_cpu uut (
+    .clk(clk)
+);
+
+initial begin
+    $display("Start testing risc 16bit cpu");
+    $dumpfile("test_risc_16bit_cpu.vcd");
+    $dumpvars(0,test_risc_16bit_cpu);
+
+
+    clk <=0;
+    `simulation_time;
+    $finish;
+end
+
+always begin
+        #5 clk = ~clk;
+end
+
+endmodule
\ No newline at end of file
-- 
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