`timescale 1ns/1ps

module test_contorl_unit;

reg [3:0] opcode;
reg[1:0] alu_op;
reg jump, bne, beq, mem_read, mem_write, alu_src, reg_dst, mem_to_reg, reg_write;

initial begin 
    $display("Start testing data path");
    $dumpfile("test_control_unit.vcd");
    $dumpvars(0,test_contorl_unit);
end



initial begin
    $monitor("At time=%t",$time);
end

endmodule