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title: STM32F4 sdram configuration
keywords:c,stm32,stm32f4,sdram,configuration,timing
# STM32F4 sdram configuration
Here is some notes about playing with SDRAM. Some parts are still unclear for
me but looks like all code works.
STM32 F4 family have build in FMC controller that can be configured to use
SDRAM with easy.
F4 have 2 internals banks and memory ranges where SDRAM could be configured.
## SDRAM parameters
## STM32 SDRAM FMC params
STM32F4 SDRAM FMC(Flexible Memory Controller) have many parameters that allow
to configure SDRAM, depending on chip you can have more or less memory available
different clock speeds.
| Struct field name | Possible values | Comments |
|---|---|---|
| SDBank | BANK1,BANK2 | |
| ColumnBitsNumber | 8-11 bits | |
| RowBitsNumber | 11-13 bits | |
| MemoryDataWidth | 8,16,32 bits | |
| CASLatency | 1,2,3 | |
| WriteProtection | ENABLE,DISABLE | |
| SDClockPeriod | DISABLE, PERIOD2, PERIOD3 | If system clock 180Mhz then CLK speeds 90Mhz or 60Mhz |
| ReadBurst | ENABLE,DISABLE | |
| ReadPipeDelay | DELAY_0, DELAY_1, DELAY_2 | |
## Configure FMC SDRAM timings
Timing configuration configured in FMC_SDTR1 register
| Struct field name | RegisterPossible Values | Register bit names |
|---|---|---|
| LoadToActiveDelay | 1-16 cycles | TMRD |
| ExitSlefRedreshDelay | 1-16 cycles | TXSR |
| SelfRefreshTime | 1-16 cycles | TRAS |
| RowCycleDelay | 1-16 cycles | TRC |
| WriteRecoveryTime | 1-16 cycles | TWR |
| RPDelay | 1-16 cycles | TRCD |
| RCDelay | 1-16 cycles | TRC |
## SDRAM initialization
Before SDRAM could start working it need to be configured and commended are
sended. Command are just setting up appropriate bits and wait of 100ms.
Commands for configure SDRAM
| Command | Desc |
|---|---|
| FMC_SDRAM_CMD_CLK_ENABLE | Configure a clock configuration enable command |
| FMC_SDRAM_CMD_PALL | Configure a PALL (precharge all) command |
| FMC_SDRAM_CMD_AUTOREFRESH_MODE | Configure a Auto-Refresh command |
| FMC_SDRAM_CMD_LOAD_MODE | Program the external memory mode register |
```c
FMC_SDRAM_CommandTypeDef Command;
__IO uint32_t tmpmrd =0;
/* Step 3: Configure a clock configuration enable command */
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command.AutoRefreshNumber = 1;
Command.ModeRegisterDefinition = 0;
/* Send the command */
HAL_SDRAM_SendCommand(hsdram, &Command, 0x1000);
/* Step 4: Insert 100 ms delay */
HAL_Delay(100);
/* Step 5: Configure a PALL (precharge all) command */
Command.CommandMode = FMC_SDRAM_CMD_PALL;
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command.AutoRefreshNumber = 1;
Command.ModeRegisterDefinition = 0;
/* Send the command */
HAL_SDRAM_SendCommand(hsdram, &Command, 0x1000);
/* Step 6 : Configure a Auto-Refresh command */
Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command.AutoRefreshNumber = 4;
Command.ModeRegisterDefinition = 0;
/* Send the command */
HAL_SDRAM_SendCommand(hsdram, &Command, 0x1000);
/* Step 7: Program the external memory mode register */
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
SDRAM_MODEREG_CAS_LATENCY_3 |
SDRAM_MODEREG_OPERATING_MODE_STANDARD |
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command.AutoRefreshNumber = 1;
Command.ModeRegisterDefinition = tmpmrd;
/* Send the command */
HAL_SDRAM_SendCommand(hsdram, &Command, 0x1000);
HAL_SDRAM_ProgramRefreshRate(hsdram, 0x56A-20);
```
### Command list for AS4C16M16SA
| Commands |
|---|
| BankActive |
| BankPrecharge |
| PrechargeAll |
| Read |
| Read and AutoPrecharge |
| Write |
| Write and AutoPrecharge |
| Mode Register Set |
| No-Operation |
| Burst Stop |
| Devaise Deselect |
| AutoRefresh |
| SelfRefresh Entry |
| SelfRedresh Exit |
| Clock Suspend Mode Entry / PowerDown Mode Entry |
| Clock Suspend Mode Exit / PowerDown Mode Exit |
| Data Write / Output Enable |
## Calculate parameters
### AS4C16M16SA chip parameters
Configuration for SystemClock=180Mhz and SDRAM clock rate 90Mhz.
Some values are adjusted to work.
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All resulting values are rounded up.
| Param in Datasheet | Param | Calc(cycles) |
|---|---|---|
| 12u | TMRD | 1(1.1)+2 ???|
| tRC+tIS = 61.5u | TXSR | 6(5.5)+1 ???|
| 42u | TRAS | 4(3.8)+1 ???|
| 60u | TRC | 6(5.5) |
| 12u | TWR | 2(1.1) |
| 18u | TRP | 2(1.6) |
| 18u | TRCD | 2(1.6) |
This what worked for me, so should be right (maybe)
Configuration for SystemClock=180Mhz and SDRAM clock rate 60Mhz
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| Param in Datasheet | Param | Calc(cycles) |
|---|---|---|
| 12u | TMRD | 1(1.1)+2 ???|
| tRC+tIS = 61.5u | TXSR | 4(3.6)+1 ???|
| 42u | TRAS | 3(2.5) |
| 60u | TRC | 4(3.6)+1 ???|
| 12u | TWR | 1(0.8) |
| 18u | TRP | 1(1.1) |
| 18u | TRCD | 1(1.1) |
### Calculate refresh rate
From datasheet - 8192 refresh cycles/64ms
64ms/8192 = 7.8u
7.8u \* (90Mhz) = 702
7.8u \* (60Mhz) = 402
## Example config
Here is example config for AS4C16M16SA
```c
SDRAM->Init.SDBank = FMC_SDRAM_BANK2;
SDRAM->Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
SDRAM->Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
SDRAM->Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
SDRAM->Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
SDRAM->Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
SDRAM->Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
SDRAM->Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2; // 90Mhz
SDRAM->Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
SDRAM->Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
/* Timing configuration for 90 MHz of SDRAM clock frequency (180MHz/2) */
SDRAM_Timing->LoadToActiveDelay = 2;
SDRAM_Timing->ExitSelfRefreshDelay = 7;
SDRAM_Timing->SelfRefreshTime = 4;
SDRAM_Timing->RowCycleDelay = 7;//was 7
SDRAM_Timing->WriteRecoveryTime = 2;
SDRAM_Timing->RPDelay = 2;
SDRAM_Timing->RCDDelay = 2;
```
## Using SDRAM
```c
for (i = 0; i < SDRAM_SIZE; i++) {
*(__IO uint16_t*) (SDRAM_BANK_ADDR + 2*i) = (uint16_t)0x00;
}
```
Example of setting values into SDRAM. Accessing just like usual memory.
## Links
1. [AS4C16M16SA datasheet](https://www.alliancememory.com/wp-content/uploads/pdf/dram/256Mb-AS4C16M16SA-C&I_V3.0_March%202015.pdf)
2. [STM32F429ZI description](http://www.st.com/en/microcontrollers/stm32f429zi.html)
3. [http://en.radzio.dxp.pl/stm32f429idiscovery/sdram.html](http://en.radzio.dxp.pl/stm32f429idiscovery/sdram.html)
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