cpu8_v.git, branch master 8bit cpu implementation in verilog https://git.main.lv/cgit.cgi/cpu8_v.git/atom?h=master 2022-02-14T08:04:19+00:00 Add alu v0.1_16bit. compiles without warning risc cpu 2022-02-14T08:04:19+00:00 dianshi dianshi@main.lv 2022-02-14T08:04:19+00:00 urn:sha1:464289c73853f13f6ccc4b584503c4c09988d1a0 Add running risc 16bit cpu v0.1 2022-02-14T08:03:29+00:00 dianshi dianshi@main.lv 2022-02-14T08:03:29+00:00 urn:sha1:76593f10b0754990f154fbb3da958d696a34f2de Add datapatch v0.1 2022-02-14T07:48:24+00:00 dianshi dianshi@main.lv 2022-02-14T07:48:24+00:00 urn:sha1:f52f1af38851b784862175ff2806bda622b0ec47 Add control unit version 0.1 2022-02-13T21:34:02+00:00 dianshi dianshi@main.lv 2022-02-13T21:34:02+00:00 urn:sha1:2a54718dc842d1be84d1470827b538bdaab2cb28 Add alu_control version v0.1 2022-01-25T21:37:30+00:00 dianshi dianshi@main.lv 2022-01-25T21:37:30+00:00 urn:sha1:2cbdc8a905d6b4fac757ae6a33f75548b16f10e7 Added general purpose memory 2022-01-19T22:03:50+00:00 dianshi dianshi@main.lv 2022-01-19T22:03:50+00:00 urn:sha1:8661ed2084e8d50ef19a2827484fefd07c4f20e1 Add instruction memory 2022-01-19T22:00:08+00:00 dianshi dianshi@main.lv 2022-01-19T22:00:08+00:00 urn:sha1:f3a300ce5927cad9ecf02821b3be007f9d2af22b Added datamem with 8bytes of memory 2022-01-13T21:41:49+00:00 dianshi dianshi@main.lv 2022-01-13T21:41:49+00:00 urn:sha1:deebf92127386873cb34d46f414d31c7a69adcfe Update AND model 2022-01-05T21:13:45+00:00 dianshi dianshi@main.lv 2022-01-05T21:13:45+00:00 urn:sha1:37bd6ad2b012754fc3573f3c2529444ce8d75f36 Added ALU 2022-01-05T21:03:04+00:00 dianshi dianshi@main.lv 2022-01-05T21:03:04+00:00 urn:sha1:b623b638fe1a0189416892415a1728839768539e