1 files changed, 75 insertions, 0 deletions
diff --git a/datamem/v0.1/test_data_memory.v b/datamem/v0.1/test_data_memory.v
new file mode 100644
index 0000000..e0633c1
--- /dev/null
+++ b/datamem/v0.1/test_data_memory.v
@@ -0,0 +1,75 @@
+`timescale 1ns/1ps
+
+module test_data_memory;
+
+reg clk;
+reg [15:0]mem_access_addr;
+reg [15:0]mem_write_data;
+reg mem_write_en;
+reg mem_read;
+reg [15:0]mem_read_data;
+
+data_memory uut (
+    .clk(clk),
+    .mem_access_addr(mem_access_addr),
+    .mem_write_data(mem_write_data),
+    .mem_write_en(mem_write_en),
+    .mem_read(mem_read),
+    .mem_read_data(mem_read_data)
+);
+
+initial begin 
+    $display("Start testing data memory");
+    $dumpfile("test_data_memory.vcd");
+    $dumpvars(0,test_data_memory);
+
+    clk=0;
+    mem_write_en = 0;
+    mem_access_addr = 0;
+    mem_read = 0;
+
+    #10 clk=0;
+    mem_write_en = 0;
+    mem_access_addr = 0;
+    mem_read = 0;
+
+    #10 clk=1;
+    mem_access_addr = 1;
+    mem_read = 1;
+
+    #10 clk=0;
+    mem_access_addr = 2;
+    mem_read = 1;
+
+    #10 clk=1;
+     mem_access_addr = 3;
+
+    #10 clk=0;
+    mem_access_addr = 4;
+
+    #10 clk=1;
+    mem_access_addr = 4;
+    mem_read=0;
+
+    #10 clk=0;
+    mem_write_en=1;
+    mem_write_data=8'hAA;
+
+    #10 clk=1;
+    
+    mem_read=0;
+
+    #10 clk=0;
+    mem_write_en=0;
+    mem_read=1;
+
+
+    #10 clk=1;
+end
+
+
+initial begin
+    $monitor("At time=%t",$time);
+end
+
+endmodule
+\ No newline at end of file