Different versions of register d-flip-flop, sr-latch, all have issues, becouse of no delay, and cpu_code_reg implemented without gate logic

1 files changed, 63 insertions, 0 deletions

diff --git a/cpu8/cpu_and/cpu_and.cpp b/cpu8/cpu_and/cpu_and.cpp
new file mode 100644
index 0000000..17e5f0f
--- /dev/null
+++ b/cpu8/cpu_and/cpu_and.cpp
@@ -0,0 +1,63 @@
+#include <iostream>
+#include <iomanip>
+
+#include "systemc.h"
+
+#include "cpu_and.hpp"
+
+SC_MODULE(test_cpu_and)
+{
+	sc_signal<bool> a,b,c;
+	sc_clock TestClk;
+
+	cpu_and circ_and;
+
+	void apply_test()
+	{
+		a = 0; b = 0;
+		wait();
+		a = 1; b = 0;
+		wait();
+		a = 0; b = 1;
+		wait();
+		a = 1; b = 1;
+		wait();
+		sc_stop();
+	}
+
+	void monitor_signals()
+	{
+		cout << "Time" << endl;
+		while (true)
+		{
+			cout << std::setw(5) << sc_time_stamp() << " ";
+			cout << std::setw(2) << a.read() << " ";
+			cout << std::setw(2) << b.read() << " ";
+			cout << std::setw(2) << c.read() << " ";
+			cout << endl;
+			wait();
+		}
+	}
+
+	SC_CTOR(test_cpu_and):
+	TestClk("TestClk", 10, SC_NS),
+	circ_and("cpu_AND") 
+	{
+		circ_and.in_a(a);
+		circ_and.in_b(b);
+		circ_and.out_c(c);
+		SC_THREAD(monitor_signals);
+		sensitive << TestClk;
+		SC_THREAD(apply_test);
+		sensitive << TestClk;
+		
+	}
+};
+
+int sc_main(int argc, char **argv) {
+	test_cpu_and test_and("cpu_and_test");
+
+	sc_start();
+
+	return(0);
+}
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