Different versions of register d-flip-flop, sr-latch, all have issues, becouse of no delay, and cpu_code_reg implemented without gate logic

14 files changed, 598 insertions, 4 deletions

diff --git a/cpu8/cpu_and/Makefile b/cpu8/cpu_and/Makefile
new file mode 100644
index 0000000..ef0884a
--- /dev/null
+++ b/cpu8/cpu_and/Makefile
@@ -0,0 +1,9 @@
+SYSTEMC_PATH=/home/fam/downloads/source/systemc/systemc-2.3.2
+SYSTEMC_INC=$(SYSTEMC_PATH)/src
+SYSTEMC_LIB=$(SYSTEMC_PATH)/src/.libs
+
+PROJECT=cpu_and_2
+
+make:
+	g++ $(PROJECT).cpp -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB) -Wl,-rpath=$(SYSTEMC_LIB)\
+		-o $(PROJECT) -lsystemc -lm
\ No newline at end of file
diff --git a/cpu8/cpu_and/cpu_and.cpp b/cpu8/cpu_and/cpu_and.cpp
new file mode 100644
index 0000000..17e5f0f
--- /dev/null
+++ b/cpu8/cpu_and/cpu_and.cpp
@@ -0,0 +1,63 @@
+#include <iostream>
+#include <iomanip>
+
+#include "systemc.h"
+
+#include "cpu_and.hpp"
+
+SC_MODULE(test_cpu_and)
+{
+	sc_signal<bool> a,b,c;
+	sc_clock TestClk;
+
+	cpu_and circ_and;
+
+	void apply_test()
+	{
+		a = 0; b = 0;
+		wait();
+		a = 1; b = 0;
+		wait();
+		a = 0; b = 1;
+		wait();
+		a = 1; b = 1;
+		wait();
+		sc_stop();
+	}
+
+	void monitor_signals()
+	{
+		cout << "Time" << endl;
+		while (true)
+		{
+			cout << std::setw(5) << sc_time_stamp() << " ";
+			cout << std::setw(2) << a.read() << " ";
+			cout << std::setw(2) << b.read() << " ";
+			cout << std::setw(2) << c.read() << " ";
+			cout << endl;
+			wait();
+		}
+	}
+
+	SC_CTOR(test_cpu_and):
+	TestClk("TestClk", 10, SC_NS),
+	circ_and("cpu_AND") 
+	{
+		circ_and.in_a(a);
+		circ_and.in_b(b);
+		circ_and.out_c(c);
+		SC_THREAD(monitor_signals);
+		sensitive << TestClk;
+		SC_THREAD(apply_test);
+		sensitive << TestClk;
+		
+	}
+};
+
+int sc_main(int argc, char **argv) {
+	test_cpu_and test_and("cpu_and_test");
+
+	sc_start();
+
+	return(0);
+}
\ No newline at end of file
diff --git a/cpu8/cpu_and/cpu_and.hpp b/cpu8/cpu_and/cpu_and.hpp
new file mode 100644
index 0000000..0c78dc0
--- /dev/null
+++ b/cpu8/cpu_and/cpu_and.hpp
@@ -0,0 +1,25 @@
+#ifndef __SYSC_CPU_ADD_HPP
+#define __SYSC_CPU_ADD_HPP
+
+#include "systemc.h"
+
+SC_MODULE (cpu_and) 
+{
+	sc_port<sc_signal_in_if<bool>,0>  in_a;
+	sc_port<sc_signal_in_if<bool>,0>  in_b;
+	sc_port<sc_signal_out_if<bool>,0> out_c;
+
+	void do_and()
+	{
+		out_c[0]->write( in_a[0]->read() && in_b[0]->read() );
+	}
+
+	SC_CTOR(cpu_and)
+	{
+		SC_METHOD(do_and);
+		sensitive << in_a << in_b;
+	}
+
+};
+
+#endif
\ No newline at end of file
diff --git a/cpu8/cpu_and/notes.txt b/cpu8/cpu_and/notes.txt
new file mode 100644
index 0000000..62e8b7e
--- /dev/null
+++ b/cpu8/cpu_and/notes.txt
@@ -0,0 +1,24 @@
+https://www.doulos.com/knowhow/systemc/tutorial/modules_and_processes/
+https://www.doulos.com/knowhow/systemc/tutorial/debugging/
+
+
+
+
+#include "systemc.h"
+SC_MODULE(nand2)          // declare nand2 sc_module
+{
+  sc_in<bool> A, B;       // input signal ports
+  sc_out<bool> F;         // output signal ports
+
+  void do_nand2()         // a C++ function
+  {
+    F.write( !(A.read() && B.read()) );
+  }
+
+  SC_CTOR(nand2)          // constructor for nand2
+  {
+    SC_METHOD(do_nand2);  // register do_nand2 with kernel
+    sensitive << A << B;  // sensitivity list
+  }
+};
+
diff --git a/cpu8/cpu_code_reg/Makefile b/cpu8/cpu_code_reg/Makefile
new file mode 100644
index 0000000..e8c3514
--- /dev/null
+++ b/cpu8/cpu_code_reg/Makefile
@@ -0,0 +1,12 @@
+SYSTEMC_PATH=/home/fam/downloads/source/systemc/systemc-2.3.2
+SYSTEMC_INC=$(SYSTEMC_PATH)/src
+SYSTEMC_LIB=$(SYSTEMC_PATH)/src/.libs
+
+PROJECT=cpu_code_reg
+
+make:
+	g++ $(PROJECT).cpp -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB) -Wl,-rpath=$(SYSTEMC_LIB)\
+		-o $(PROJECT) -lsystemc -lm
+
+
+
diff --git a/cpu8/cpu_code_reg/cpu_code_reg.cpp b/cpu8/cpu_code_reg/cpu_code_reg.cpp
new file mode 100644
index 0000000..d312cd7
--- /dev/null
+++ b/cpu8/cpu_code_reg/cpu_code_reg.cpp
@@ -0,0 +1,82 @@
+#include <iostream>
+#include <iomanip>
+
+#include "systemc.h"
+#include "systemc"
+#include <sysc/tracing/sc_trace.h>
+#include <sysc/tracing/sc_vcd_trace.h>
+
+#include "cpu_code_reg.hpp"
+
+SC_MODULE(test_cpu_code_reg)
+{
+	sc_out<bool> d,e;
+	sc_in<bool> clk;
+
+	void test_cpu_reg_stim()
+	{
+		wait();
+		d.write(0);
+		e.write(0);
+
+		wait();
+		d.write(1);
+		e.write(0);
+
+		wait();
+		d.write(0);
+		e.write(1);
+
+		wait();
+		d.write(1);
+		e.write(1);
+
+		wait();
+		d.write(0);
+		e.write(0);
+
+		wait();
+		d.write(1);
+		e.write(0);
+
+		wait();
+
+		sc_stop();
+	}
+
+	SC_CTOR(test_cpu_code_reg)
+	{
+		SC_THREAD(test_cpu_reg_stim);
+		sensitive << clk.pos();
+
+	}
+};
+
+
+int sc_main(int argc, char **argv) {
+	int i;
+	sc_signal<bool> sig_in_d,sig_in_e, sig_out_q;
+	sc_clock TestClk("TestClk", 10, SC_NS, 0.5, 1, SC_NS);
+
+	test_cpu_code_reg Stim1("Stimulus");
+	Stim1.e(sig_in_e);
+	Stim1.d(sig_in_d);
+	Stim1.clk(TestClk);
+
+	cpu_code_reg DUT("cpu_code_eg");
+	DUT.in_d(sig_in_d);
+	DUT.in_e(sig_in_e);
+	DUT.out_q(sig_out_q);
+
+	sc_trace_file *Tf;
+	
+	Tf = sc_create_vcd_trace_file("trace_cpu_code_reg.dat");
+	sc_trace(Tf, sig_in_d, "D");
+	sc_trace(Tf, sig_in_e, "E");
+	sc_trace(Tf, sig_out_q, "Q");
+
+	sc_start();
+	sc_close_vcd_trace_file(Tf);
+
+	return(0);
+}
\ No newline at end of file
diff --git a/cpu8/cpu_code_reg/cpu_code_reg.hpp b/cpu8/cpu_code_reg/cpu_code_reg.hpp
new file mode 100644
index 0000000..c48a256
--- /dev/null
+++ b/cpu8/cpu_code_reg/cpu_code_reg.hpp
@@ -0,0 +1,39 @@
+#ifndef __SYSC_CPU_CODE_REG_HPP
+#define __SYSC_CPU_CODE_REG_HPP
+
+#include "systemc.h"
+#include "../cpu_and/cpu_and.hpp"
+#include "../cpu_not/cpu_not.hpp"
+#include "../cpu_srlatch/cpu_srlatch.hpp"
+
+SC_MODULE (cpu_code_reg) 
+{
+	//Inputs
+	sc_port<sc_signal_in_if<bool>,0> in_d;
+	sc_port<sc_signal_in_if<bool>,0> in_e;
+	//Outputs
+	sc_port<sc_signal_out_if<bool>,0> out_q;
+	//Internal variables
+	bool bit=false;
+
+	void do_code_reg()
+	{
+		//if enabled
+		if (in_e[0]->read())
+		{
+			//set data
+			bit = in_d[0]->read();
+		}
+		//no delay
+		out_q[0]->write(bit);
+	}
+
+	SC_CTOR(cpu_code_reg)
+	{	
+		SC_METHOD(do_code_reg);
+		sensitive << in_d << in_e;
+	}
+
+};
+
+#endif
\ No newline at end of file
diff --git a/cpu8/cpu_gatedlatch/Makefile b/cpu8/cpu_gatedlatch/Makefile
new file mode 100644
index 0000000..8fa3701
--- /dev/null
+++ b/cpu8/cpu_gatedlatch/Makefile
@@ -0,0 +1,12 @@
+SYSTEMC_PATH=/home/fam/downloads/source/systemc/systemc-2.3.2
+SYSTEMC_INC=$(SYSTEMC_PATH)/src
+SYSTEMC_LIB=$(SYSTEMC_PATH)/src/.libs
+
+PROJECT=cpu_gatedlatch
+
+make:
+	g++ $(PROJECT).cpp -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB) -Wl,-rpath=$(SYSTEMC_LIB)\
+		-o $(PROJECT) -lsystemc -lm
+
+
+
diff --git a/cpu8/cpu_gatedlatch/cpu_gatedlatch.cpp b/cpu8/cpu_gatedlatch/cpu_gatedlatch.cpp
new file mode 100644
index 0000000..b489e5b
--- /dev/null
+++ b/cpu8/cpu_gatedlatch/cpu_gatedlatch.cpp
@@ -0,0 +1,96 @@
+#include <iostream>
+#include <iomanip>
+
+#include "systemc.h"
+#include "systemc"
+#include <sysc/tracing/sc_trace.h>
+#include <sysc/tracing/sc_vcd_trace.h>
+
+#include "cpu_gatedlatch.hpp"
+
+SC_MODULE(test_cpu_gatedlatch)
+{
+	sc_out<bool> d,e;
+	sc_in<bool> clk;
+
+	void test_cpu_gatedlatch_stim()
+	{
+		wait();
+		d.write(0);
+		e.write(0);
+
+		wait();
+		d.write(1);
+		e.write(0);
+
+		wait();
+		d.write(0);
+		e.write(1);
+
+		wait();
+		d.write(1);
+		e.write(1);
+
+		wait();
+		d.write(0);
+		e.write(0);
+
+		wait();
+		d.write(1);
+		e.write(0);
+
+		wait();
+		d.write(0);
+		e.write(1);
+
+		wait();
+		d.write(0);
+		e.write(0);
+
+
+		wait();
+
+		sc_stop();
+	}
+
+	SC_CTOR(test_cpu_gatedlatch)
+	{
+		SC_THREAD(test_cpu_gatedlatch_stim);
+		sensitive << clk.pos();
+
+	}
+};
+
+
+int sc_main(int argc, char **argv) {
+	int i;
+	sc_signal<bool> sig_in_d,sig_in_e, sig_out_q, sig_out_nq;
+	sc_clock TestClk("TestClk", 10, SC_NS, 0.5, 1, SC_NS);
+
+	test_cpu_gatedlatch Stim1("Stimulus");
+	Stim1.e(sig_in_e);
+	Stim1.d(sig_in_d);
+	Stim1.clk(TestClk);
+
+
+	
+	cpu_gatedlatch DUT("cpu_gatedlatch");
+	DUT.in_d(sig_in_d);
+	DUT.in_e(sig_in_e);
+	DUT.out_q(sig_out_q);
+	DUT.out_nq(sig_out_nq);
+
+	
+	sc_trace_file *Tf;
+	
+	Tf = sc_create_vcd_trace_file("trace_cpu_gatedlatch.dat");
+	sc_trace(Tf, sig_in_d, "D");
+	sc_trace(Tf, sig_in_e, "E");
+	sc_trace(Tf, sig_out_q, "Q");
+	sc_trace(Tf, sig_out_nq, "NQ");
+
+	sc_start();
+	sc_close_vcd_trace_file(Tf);
+
+	return(0);
+}
\ No newline at end of file
diff --git a/cpu8/cpu_gatedlatch/cpu_gatedlatch.hpp b/cpu8/cpu_gatedlatch/cpu_gatedlatch.hpp
new file mode 100644
index 0000000..d3f314f
--- /dev/null
+++ b/cpu8/cpu_gatedlatch/cpu_gatedlatch.hpp
@@ -0,0 +1,63 @@
+#ifndef __SYSC_CPU_GATEDLATCH_HPP
+#define __SYSC_CPU_GATEDLATCH_HPP
+
+#include "systemc.h"
+#include "../cpu_nand/cpu_nand.hpp"
+
+SC_MODULE (cpu_gatedlatch) 
+{
+	//Inputs
+	sc_in <bool> in_d;
+	sc_in <bool> in_e;
+	sc_out <bool> out_q,out_nq;
+
+	cpu_nand *nand1, *nand2, *nand3, *nand4, *nand5;
+
+	sc_signal<bool> sig_nand1nand3;
+	sc_signal<bool> sig_nand2nand4;
+	sc_signal<bool> sig_nand3nand5;
+	sc_signal<bool> sig_qnand5, sig_nqnand4;
+
+	void do_gatedlatch()
+	{
+
+	}
+
+	SC_CTOR(cpu_gatedlatch)
+	{
+
+		nand1 = new cpu_nand("NAND1");
+		nand2 = new cpu_nand("NAND2");
+		nand3 = new cpu_nand("NAND3");
+		nand4 = new cpu_nand("NAND4");
+		nand5 = new cpu_nand("NAND5");
+
+		nand1->in_a(in_d);
+		nand1->in_b(in_d);
+		nand1->out_c(sig_nand1nand3);
+
+		nand2->in_a(in_d);
+		nand2->in_b(in_e);
+		nand2->out_c(sig_nand2nand4);
+
+		nand3->in_a(in_e);
+		nand3->in_b(sig_nand1nand3);
+		nand3->out_c(sig_nand3nand5);
+
+		nand4->in_a(sig_nand2nand4);
+		nand4->in_b(sig_nqnand4);
+		nand4->out_c(out_q);
+		nand4->out_c(sig_qnand5);
+
+		nand5->in_a(sig_qnand5);
+		nand5->in_b(sig_nand3nand5);
+		nand5->out_c(out_nq);
+		nand5->out_c(sig_nqnand4);
+
+		//SC_METHOD(do_gatedlatch);
+		//sensitive << in_d << in_clk;
+	}
+
+};
+
+#endif
\ No newline at end of file
diff --git a/cpu8/cpu_nand/cpu_nand.hpp b/cpu8/cpu_nand/cpu_nand.hpp
index 5e5e517..8194998 100644
--- a/cpu8/cpu_nand/cpu_nand.hpp
+++ b/cpu8/cpu_nand/cpu_nand.hpp
@@ -5,13 +5,13 @@
 
 SC_MODULE (cpu_nand) 
 {
-	sc_in <bool> in_a;
-	sc_in <bool> in_b;
-	sc_out <bool> out_c;
+	sc_port<sc_signal_in_if<bool>,0> in_a;
+	sc_port<sc_signal_in_if<bool>,0> in_b;
+	sc_port<sc_signal_out_if<bool>,0> out_c;
 
 	void do_nand()
 	{
-		out_c.write( !(in_a.read() && in_b.read()) );
+		out_c[0]->write( !(in_a[0]->read() && in_b[0]->read()) );
 	}
 
 	SC_CTOR(cpu_nand)
diff --git a/cpu8/cpu_reg/Makefile b/cpu8/cpu_reg/Makefile
new file mode 100644
index 0000000..c37accb
--- /dev/null
+++ b/cpu8/cpu_reg/Makefile
@@ -0,0 +1,12 @@
+SYSTEMC_PATH=/home/fam/downloads/source/systemc/systemc-2.3.2
+SYSTEMC_INC=$(SYSTEMC_PATH)/src
+SYSTEMC_LIB=$(SYSTEMC_PATH)/src/.libs
+
+PROJECT=cpu_reg
+
+make:
+	g++ $(PROJECT).cpp -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB) -Wl,-rpath=$(SYSTEMC_LIB)\
+		-o $(PROJECT) -lsystemc -lm
+
+
+
diff --git a/cpu8/cpu_reg/cpu_reg.cpp b/cpu8/cpu_reg/cpu_reg.cpp
new file mode 100644
index 0000000..17f4a72
--- /dev/null
+++ b/cpu8/cpu_reg/cpu_reg.cpp
@@ -0,0 +1,96 @@
+#include <iostream>
+#include <iomanip>
+
+#include "systemc.h"
+#include "systemc"
+#include <sysc/tracing/sc_trace.h>
+#include <sysc/tracing/sc_vcd_trace.h>
+
+#include "cpu_reg.hpp"
+
+SC_MODULE(test_cpu_reg)
+{
+	sc_out<bool> d,e;
+	sc_in<bool> clk;
+
+	void test_cpu_reg_stim()
+	{
+		wait();
+		d.write(0);
+		e.write(0);
+
+		wait();
+		d.write(1);
+		e.write(0);
+
+		wait();
+		d.write(0);
+		e.write(1);
+
+		wait();
+		d.write(1);
+		e.write(1);
+
+		wait();
+		d.write(0);
+		e.write(0);
+
+		wait();
+		d.write(1);
+		e.write(0);
+
+		wait();
+		d.write(0);
+		e.write(1);
+
+		wait();
+		d.write(0);
+		e.write(0);
+
+
+		wait();
+
+		sc_stop();
+	}
+
+	SC_CTOR(test_cpu_reg)
+	{
+		SC_THREAD(test_cpu_reg_stim);
+		sensitive << clk.pos();
+
+	}
+};
+
+
+int sc_main(int argc, char **argv) {
+	int i;
+	sc_signal<bool> sig_in_d,sig_in_e, sig_out_q, sig_out_nq;
+	sc_clock TestClk("TestClk", 10, SC_NS, 0.5, 1, SC_NS);
+
+	test_cpu_reg Stim1("Stimulus");
+	Stim1.e(sig_in_e);
+	Stim1.d(sig_in_d);
+	Stim1.clk(TestClk);
+
+
+	
+	cpu_reg DUT("cpu_reg");
+	DUT.in_d(sig_in_d);
+	DUT.in_e(sig_in_e);
+	DUT.out_q(sig_out_q);
+	DUT.out_nq(sig_out_nq);
+
+	
+	sc_trace_file *Tf;
+	
+	Tf = sc_create_vcd_trace_file("trace_cpu_reg.dat");
+	sc_trace(Tf, sig_in_d, "D");
+	sc_trace(Tf, sig_in_e, "E");
+	sc_trace(Tf, sig_out_q, "Q");
+	sc_trace(Tf, sig_out_nq, "NQ");
+
+	sc_start();
+	sc_close_vcd_trace_file(Tf);
+
+	return(0);
+}
\ No newline at end of file
diff --git a/cpu8/cpu_reg/cpu_reg.hpp b/cpu8/cpu_reg/cpu_reg.hpp
new file mode 100644
index 0000000..15e2a3e
--- /dev/null
+++ b/cpu8/cpu_reg/cpu_reg.hpp
@@ -0,0 +1,61 @@
+#ifndef __SYSC_CPU_REG_HPP
+#define __SYSC_CPU_REG_HPP
+
+#include "systemc.h"
+#include "../cpu_and/cpu_and.hpp"
+#include "../cpu_not/cpu_not.hpp"
+#include "../cpu_srlatch/cpu_srlatch.hpp"
+
+SC_MODULE (cpu_reg) 
+{
+	//Inputs
+	sc_in <bool> in_d;
+	sc_in <bool> in_e;
+	sc_in <bool> in_r;
+	sc_out <bool> out_q,out_nq;
+
+	cpu_and *and1, *and2;
+	cpu_not *not1;
+	cpu_srlatch *srlatch1;
+
+	sc_signal<bool> sig_not1and1;
+	sc_signal<bool> sig_and1srlatch1;
+	sc_signal<bool> sig_and2srlatch1;
+
+	void do_reg()
+	{
+
+	}
+
+	SC_CTOR(cpu_reg)
+	{
+
+		and1 = new cpu_and("AND1");
+		and2 = new cpu_and("AND2");
+		not1 = new cpu_not("NOT1");
+		srlatch1 = new cpu_srlatch("SRLATCH1");
+
+		
+		and1->in_a(sig_not1and1);
+		and1->in_b(in_e);
+		and1->out_c(sig_and1srlatch1);
+
+		and2->in_a(in_d);
+		and2->in_b(in_e);
+		and2->out_c(sig_and2srlatch1);
+
+		not1->in_a(in_d);
+		not1->out_b(sig_not1and1);
+
+		srlatch1->in_r(sig_and1srlatch1);
+		srlatch1->in_s(sig_and2srlatch1);
+		srlatch1->out_q(out_q);
+		srlatch1->out_nq(out_nq);
+		
+		//SC_METHOD(do_reg);
+		//sensitive << in_d << in_clk;
+	}
+
+};
+
+#endif
\ No newline at end of file