Added initial CPU SR-latch

3 files changed, 165 insertions, 0 deletions

diff --git a/cpu8/cpu_srlatch/Makefile b/cpu8/cpu_srlatch/Makefile
new file mode 100644
index 0000000..acccab7
--- /dev/null
+++ b/cpu8/cpu_srlatch/Makefile
@@ -0,0 +1,12 @@
+SYSTEMC_PATH=/home/fam/downloads/source/systemc/systemc-2.3.2
+SYSTEMC_INC=$(SYSTEMC_PATH)/src
+SYSTEMC_LIB=$(SYSTEMC_PATH)/src/.libs
+
+PROJECT=cpu_srlatch
+
+make:
+	g++ $(PROJECT).cpp -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB) -Wl,-rpath=$(SYSTEMC_LIB)\
+		-o $(PROJECT) -lsystemc -lm
+
+
+
diff --git a/cpu8/cpu_srlatch/cpu_srlatch.cpp b/cpu8/cpu_srlatch/cpu_srlatch.cpp
new file mode 100644
index 0000000..07efe5e
--- /dev/null
+++ b/cpu8/cpu_srlatch/cpu_srlatch.cpp
@@ -0,0 +1,98 @@
+#include <iostream>
+#include <iomanip>
+
+#include "systemc.h"
+#include "systemc"
+#include <sysc/tracing/sc_trace.h>
+#include <sysc/tracing/sc_vcd_trace.h>
+
+#include "cpu_srlatch.hpp"
+
+SC_MODULE(test_cpu_srlatch)
+{
+	sc_out<bool> s,r;
+	sc_in<bool> clk;
+	
+
+	void test_cpu_srlatch_stim()
+	{
+		wait();
+		s.write(0);
+		r.write(1);
+
+		wait();
+		s.write(1);
+		r.write(0);
+
+		wait();
+		s.write(1);
+		r.write(1);
+
+		wait();
+		s.write(1);
+		r.write(0);
+
+		wait();
+		s.write(0);
+		r.write(0);
+
+
+		wait();
+		s.write(0);
+		r.write(0);
+
+		wait();
+		s.write(0);
+		r.write(1);
+
+		wait();
+		s.write(0);
+		r.write(0);
+
+		wait();
+		s.write(0);
+		r.write(0);
+
+
+		wait();
+
+		sc_stop();
+	}
+
+	SC_CTOR(test_cpu_srlatch)
+	{
+		SC_THREAD(test_cpu_srlatch_stim);
+		sensitive << clk.pos();
+
+	}
+};
+
+
+int sc_main(int argc, char **argv) {
+	sc_signal<bool> sig_in_r, sig_in_s, sig_out_q, sig_out_nq;
+	sc_clock TestClk("TestClk", 10, SC_NS, 0.5, 1, SC_NS);
+
+	test_cpu_srlatch Stim1("Stimulus");
+	Stim1.r(sig_in_r);
+	Stim1.s(sig_in_s);
+	Stim1.clk(TestClk);
+
+	cpu_srlatch DUT("cpu_srlatch");
+	DUT.in_r(sig_in_r);
+	DUT.in_s(sig_in_s);
+	DUT.out_q(sig_out_q);
+	DUT.out_nq(sig_out_nq);
+
+	sc_trace_file *Tf;
+	
+	Tf = sc_create_vcd_trace_file("trace_cpu_srlatch.dat");
+	sc_trace(Tf, sig_in_r, "IN_R");
+	sc_trace(Tf, sig_in_s, "IN_S");
+	sc_trace(Tf, sig_out_q, "OUT_Q");
+	sc_trace(Tf, sig_out_nq, "OUT_NQ");
+
+	sc_start();
+	sc_close_vcd_trace_file(Tf);
+
+	return(0);
+}
\ No newline at end of file
diff --git a/cpu8/cpu_srlatch/cpu_srlatch.hpp b/cpu8/cpu_srlatch/cpu_srlatch.hpp
new file mode 100644
index 0000000..f495e70
--- /dev/null
+++ b/cpu8/cpu_srlatch/cpu_srlatch.hpp
@@ -0,0 +1,55 @@
+#ifndef __SYSC_CPU_SRLATCH_HPP
+#define __SYSC_CPU_SRLATCH_HPP
+
+#include "systemc.h"
+#include "../cpu_or/cpu_or.hpp"
+#include "../cpu_not/cpu_not.hpp"
+
+SC_MODULE (cpu_srlatch) 
+{
+	//Inputs
+	sc_in <bool> in_r;
+	sc_in <bool> in_s;
+	sc_out <bool> out_q,out_nq;
+
+	cpu_or *or1,*or2;
+	cpu_not *not1, *not2;
+
+	sc_signal<bool,SC_MANY_WRITERS> sig_or1not1, sig_or2not2;
+	sc_signal<bool,SC_MANY_WRITERS> sig_outq_ins, sig_outnq_inr;
+
+	void do_srlatch()
+	{
+		
+	}
+
+	SC_CTOR(cpu_srlatch)
+	{
+		or1 = new cpu_or("OR1");
+		or2 = new cpu_or("OR2");
+		not1 = new cpu_not("NOT1");
+		not2 = new cpu_not("NOT2");
+
+		or1->in_a(in_r);
+		or1->in_b(sig_outnq_inr);
+		or1->out_c(sig_or1not1);
+
+		or2->in_a(sig_outq_ins);
+		or2->in_b(in_s);
+		or2->out_c(sig_or2not2);
+
+		not1->in_a(sig_or1not1);
+		not1->out_b(out_q);
+		not1->out_b(sig_outq_ins);
+
+		not2->in_a(sig_or2not2);
+		not2->out_b(out_nq);
+		not2->out_b(sig_outnq_inr);
+
+		//SC_METHOD(do_srlatch);
+		//sensitive << in_r << in_s;
+	}
+
+};
+
+#endif
\ No newline at end of file