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| author | FreeArtMan <dos21h@gmail.com> | 2018-12-04 21:22:39 +0000 |
|---|---|---|
| committer | FreeArtMan <dos21h@gmail.com> | 2018-12-04 21:22:39 +0000 |
| commit | 3e1eb700dd4fc8dc47772ff7942990e61dcde32e (patch) | |
| tree | 18cc811e52e9da514cea531ec70c652250be8ccd /cpu8/cpu_nand/cpu_nand.hpp | |
| parent | 7e00e4960af68e6c26104cca26cdf47f4f4095a7 (diff) | |
| download | cpu8-3e1eb700dd4fc8dc47772ff7942990e61dcde32e.tar.gz cpu8-3e1eb700dd4fc8dc47772ff7942990e61dcde32e.zip | |
Different versions of register d-flip-flop, sr-latch, all have issues, becouse of no delay, and cpu_code_reg implemented without gate logic
Diffstat (limited to 'cpu8/cpu_nand/cpu_nand.hpp')
| -rw-r--r-- | cpu8/cpu_nand/cpu_nand.hpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/cpu8/cpu_nand/cpu_nand.hpp b/cpu8/cpu_nand/cpu_nand.hpp index 5e5e517..8194998 100644 --- a/cpu8/cpu_nand/cpu_nand.hpp +++ b/cpu8/cpu_nand/cpu_nand.hpp @@ -5,13 +5,13 @@ SC_MODULE (cpu_nand) { - sc_in <bool> in_a; - sc_in <bool> in_b; - sc_out <bool> out_c; + sc_port<sc_signal_in_if<bool>,0> in_a; + sc_port<sc_signal_in_if<bool>,0> in_b; + sc_port<sc_signal_out_if<bool>,0> out_c; void do_nand() { - out_c.write( !(in_a.read() && in_b.read()) ); + out_c[0]->write( !(in_a[0]->read() && in_b[0]->read()) ); } SC_CTOR(cpu_nand) |