Different versions of register d-flip-flop, sr-latch, all have issues, becouse of no delay, and cpu_code_reg implemented without gate logic

1 files changed, 61 insertions, 0 deletions

diff --git a/cpu8/cpu_reg/cpu_reg.hpp b/cpu8/cpu_reg/cpu_reg.hpp
new file mode 100644
index 0000000..15e2a3e
--- /dev/null
+++ b/cpu8/cpu_reg/cpu_reg.hpp
@@ -0,0 +1,61 @@
+#ifndef __SYSC_CPU_REG_HPP
+#define __SYSC_CPU_REG_HPP
+
+#include "systemc.h"
+#include "../cpu_and/cpu_and.hpp"
+#include "../cpu_not/cpu_not.hpp"
+#include "../cpu_srlatch/cpu_srlatch.hpp"
+
+SC_MODULE (cpu_reg) 
+{
+	//Inputs
+	sc_in <bool> in_d;
+	sc_in <bool> in_e;
+	sc_in <bool> in_r;
+	sc_out <bool> out_q,out_nq;
+
+	cpu_and *and1, *and2;
+	cpu_not *not1;
+	cpu_srlatch *srlatch1;
+
+	sc_signal<bool> sig_not1and1;
+	sc_signal<bool> sig_and1srlatch1;
+	sc_signal<bool> sig_and2srlatch1;
+
+	void do_reg()
+	{
+
+	}
+
+	SC_CTOR(cpu_reg)
+	{
+
+		and1 = new cpu_and("AND1");
+		and2 = new cpu_and("AND2");
+		not1 = new cpu_not("NOT1");
+		srlatch1 = new cpu_srlatch("SRLATCH1");
+
+		
+		and1->in_a(sig_not1and1);
+		and1->in_b(in_e);
+		and1->out_c(sig_and1srlatch1);
+
+		and2->in_a(in_d);
+		and2->in_b(in_e);
+		and2->out_c(sig_and2srlatch1);
+
+		not1->in_a(in_d);
+		not1->out_b(sig_not1and1);
+
+		srlatch1->in_r(sig_and1srlatch1);
+		srlatch1->in_s(sig_and2srlatch1);
+		srlatch1->out_q(out_q);
+		srlatch1->out_nq(out_nq);
+		
+		//SC_METHOD(do_reg);
+		//sensitive << in_d << in_clk;
+	}
+
+};
+
+#endif
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