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author | dianshi <dianshi@main.lv> | 2022-01-25 21:37:30 +0000 |
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committer | dianshi <dianshi@main.lv> | 2022-01-25 21:37:30 +0000 |
commit | 2cbdc8a905d6b4fac757ae6a33f75548b16f10e7 (patch) | |
tree | 138402f00d7e675e8c6bc80a66d56a7e8b7c7c58 /alu_control/v0.1 | |
parent | 8661ed2084e8d50ef19a2827484fefd07c4f20e1 (diff) | |
download | cpu8_v-2cbdc8a905d6b4fac757ae6a33f75548b16f10e7.tar.gz cpu8_v-2cbdc8a905d6b4fac757ae6a33f75548b16f10e7.zip |
Add alu_control version v0.1
Diffstat (limited to 'alu_control/v0.1')
-rw-r--r-- | alu_control/v0.1/Makefile | 9 | ||||
-rw-r--r-- | alu_control/v0.1/alu_control.v | 26 | ||||
-rw-r--r-- | alu_control/v0.1/test_alu_control.v | 74 |
3 files changed, 109 insertions, 0 deletions
diff --git a/alu_control/v0.1/Makefile b/alu_control/v0.1/Makefile new file mode 100644 index 0000000..ce574d3 --- /dev/null +++ b/alu_control/v0.1/Makefile @@ -0,0 +1,9 @@ +make: + iverilog -g2005-sv -o alu_control alu_control.v + iverilog -g2005-sv -o test_alu_control test_alu_control.v alu_control.v + +test: + vvp test_alu_control + +wave: + gtkwave test_alu_control.vcd diff --git a/alu_control/v0.1/alu_control.v b/alu_control/v0.1/alu_control.v new file mode 100644 index 0000000..fb6a743 --- /dev/null +++ b/alu_control/v0.1/alu_control.v @@ -0,0 +1,26 @@ +module alu_control( + input [1:0] alu_op, + input [3:0] opcode, + output reg [2:0] alu_cnt + +); + +wire [5:0]alu_control_in; +assign alu_control_in = {alu_op, opcode}; + +always @(alu_control_in) +casex (alu_control_in) + 6'b10xxxx: alu_cnt=3'b000; + 6'b01xxxx: alu_cnt=3'b001; + 6'b000010: alu_cnt=3'b000; + 6'b000011: alu_cnt=3'b001; + 6'b000100: alu_cnt=3'b010; + 6'b000101: alu_cnt=3'b011; + 6'b000110: alu_cnt=3'b100; + 6'b000111: alu_cnt=3'b101; + 6'b001000: alu_cnt=3'b110; + 6'b001001: alu_cnt=3'b111; + default: alu_cnt=3'b000; +endcase + +endmodule
\ No newline at end of file diff --git a/alu_control/v0.1/test_alu_control.v b/alu_control/v0.1/test_alu_control.v new file mode 100644 index 0000000..878744a --- /dev/null +++ b/alu_control/v0.1/test_alu_control.v @@ -0,0 +1,74 @@ +`timescale 1ns/1ps + +module test_alu_control; + +reg [1:0]alu_op; +reg [3:0]opcode; +reg [2:0]alu_cnt; + +alu_control uut( + .alu_op(alu_op), + .opcode(opcode), + .alu_cnt(alu_cnt) +); + +initial begin + $display("test alu control"); + $dumpfile("test_alu_control.vcd"); + $dumpvars(0,test_alu_control); + + #1 + alu_op = 0; + opcode = 0; + + #10 + + opcode = 1; + + #10 + + opcode = 2; + + #10 + + opcode = 3; + + #10 + + opcode = 4; + + #10 + + opcode = 5; + + #10 + + opcode = 6; + + #10 + + opcode = 7; + + #10 + alu_op = 1; + opcode = 0; + + #10 + alu_op = 2; + opcode = 1; + + #10 + alu_op = 3; + + #10 + alu_op = 3; + + +end + + +initial begin + $monitor("At time %t",$time); +end + +endmodule
\ No newline at end of file |