Add control unit version 0.1

3 files changed, 224 insertions, 0 deletions

diff --git a/control_unit/v0.1/Makefile b/control_unit/v0.1/Makefile
new file mode 100644
index 0000000..a054e3d
--- /dev/null
+++ b/control_unit/v0.1/Makefile
@@ -0,0 +1,8 @@
+make:
+	iverilog -g2005-sv -o control_unit control_unit.v
+	iverilog -g2005-sv -o test_control_unit test_control_unit.v
+test:
+	./test_control_unit
+
+wave:
+	gtkwave test_data_path.vcd
\ No newline at end of file
diff --git a/control_unit/v0.1/control_unit.v b/control_unit/v0.1/control_unit.v
new file mode 100644
index 0000000..2fdfc14
--- /dev/null
+++ b/control_unit/v0.1/control_unit.v
@@ -0,0 +1,195 @@
+module control_unit(
+    input [3:0] opcode,
+    output reg[1:0] alu_op,
+    output reg jump, bne, beq, mem_read, mem_write, alu_src, reg_dst, mem_to_reg, reg_write   
+);
+
+always @(*)
+begin
+   case(opcode)
+    4'b0000:  // LW
+   begin
+    reg_dst = 1'b0;
+    alu_src = 1'b1;
+    mem_to_reg = 1'b1;
+    reg_write = 1'b1;
+    mem_read = 1'b1;
+    mem_write = 1'b0;
+    beq = 1'b0;
+    bne = 1'b0;
+    alu_op = 2'b10;
+    jump = 1'b0;   
+   end
+ 4'b0001:  // SW
+   begin
+    reg_dst = 1'b0;
+    alu_src = 1'b1;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b0;
+    mem_read = 1'b0;
+    mem_write = 1'b1;
+    beq = 1'b0;
+    bne = 1'b0;
+    alu_op = 2'b10;
+    jump = 1'b0;   
+   end
+   4'b0010:  // data_processing
+   begin
+    reg_dst = 1'b1;
+    alu_src = 1'b0;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b1;
+    mem_read = 1'b0;
+    mem_write = 1'b0;
+    beq = 1'b0;
+    bne = 1'b0;
+    alu_op = 2'b00;
+    jump = 1'b0;   
+   end
+ 4'b0011:  // data_processing
+   begin
+    reg_dst = 1'b1;
+    alu_src = 1'b0;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b1;
+    mem_read = 1'b0;
+    mem_write = 1'b0;
+    beq = 1'b0;
+    bne = 1'b0;
+    alu_op = 2'b00;
+    jump = 1'b0;   
+   end
+     4'b0100:  // data_processing
+   begin
+    reg_dst = 1'b1;
+    alu_src = 1'b0;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b1;
+    mem_read = 1'b0;
+    mem_write = 1'b0;
+    beq = 1'b0;
+    bne = 1'b0;
+    alu_op = 2'b00;
+    jump = 1'b0;   
+   end
+ 4'b0101:  // data_processing
+   begin
+    reg_dst = 1'b1;
+    alu_src = 1'b0;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b1;
+    mem_read = 1'b0;
+    mem_write = 1'b0;
+    beq = 1'b0;
+    bne = 1'b0;
+    alu_op = 2'b00;
+    jump = 1'b0;   
+   end
+ 4'b0110:  // data_processing
+   begin
+    reg_dst = 1'b1;
+    alu_src = 1'b0;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b1;
+    mem_read = 1'b0;
+    mem_write = 1'b0;
+    beq = 1'b0;
+    bne = 1'b0;
+    alu_op = 2'b00;
+    jump = 1'b0;   
+   end
+ 4'b0111:  // data_processing
+   begin
+    reg_dst = 1'b1;
+    alu_src = 1'b0;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b1;
+    mem_read = 1'b0;
+    mem_write = 1'b0;
+    beq = 1'b0;
+    bne = 1'b0;
+    alu_op = 2'b00;
+    jump = 1'b0;   
+   end
+ 4'b1000:  // data_processing
+   begin
+    reg_dst = 1'b1;
+    alu_src = 1'b0;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b1;
+    mem_read = 1'b0;
+    mem_write = 1'b0;
+    beq = 1'b0;
+    bne = 1'b0;
+    alu_op = 2'b00;
+    jump = 1'b0;   
+   end
+ 4'b1001:  // data_processing
+   begin
+    reg_dst = 1'b1;
+    alu_src = 1'b0;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b1;
+    mem_read = 1'b0;
+    mem_write = 1'b0;
+    beq = 1'b0;
+    bne = 1'b0;
+    alu_op = 2'b00;
+    jump = 1'b0;   
+   end
+
+    4'b1011:  // BEQ
+   begin
+    reg_dst = 1'b0;
+    alu_src = 1'b0;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b0;
+    mem_read = 1'b0;
+    mem_write = 1'b0;
+    beq = 1'b1;
+    bne = 1'b0;
+    alu_op = 2'b01;
+    jump = 1'b0;   
+   end
+ 4'b1100:  // BNE
+   begin
+    reg_dst = 1'b0;
+    alu_src = 1'b0;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b0;
+    mem_read = 1'b0;
+    mem_write = 1'b0;
+    beq = 1'b0;
+    bne = 1'b1;
+    alu_op = 2'b01;
+    jump = 1'b0;   
+   end
+    4'b1101:  // J
+   begin
+    reg_dst = 1'b0;
+    alu_src = 1'b0;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b0;
+    mem_read = 1'b0;
+    mem_write = 1'b0;
+    beq = 1'b0;
+    bne = 1'b0;
+    alu_op = 2'b00;
+    jump = 1'b1;   
+   end   
+ default: begin
+    reg_dst = 1'b1;
+    alu_src = 1'b0;
+    mem_to_reg = 1'b0;
+    reg_write = 1'b1;
+    mem_read = 1'b0;
+    mem_write = 1'b0;
+    beq = 1'b0;
+    bne = 1'b0;
+    alu_op = 2'b00;
+    jump = 1'b0; 
+   end
+ endcase
+end
+
+endmodule
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diff --git a/control_unit/v0.1/test_control_unit.v b/control_unit/v0.1/test_control_unit.v
new file mode 100644
index 0000000..2398da2
--- /dev/null
+++ b/control_unit/v0.1/test_control_unit.v
@@ -0,0 +1,21 @@
+`timescale 1ns/1ps
+
+module test_contorl_unit;
+
+reg [3:0] opcode;
+reg[1:0] alu_op;
+reg jump, bne, beq, mem_read, mem_write, alu_src, reg_dst, mem_to_reg, reg_write;
+
+initial begin 
+    $display("Start testing data path");
+    $dumpfile("test_control_unit.vcd");
+    $dumpvars(0,test_contorl_unit);
+end
+
+
+
+initial begin
+    $monitor("At time=%t",$time);
+end
+
+endmodule
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