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| author | dianshi <dianshi@main.lv> | 2022-01-19 22:00:08 +0000 |
|---|---|---|
| committer | dianshi <dianshi@main.lv> | 2022-01-19 22:00:08 +0000 |
| commit | f3a300ce5927cad9ecf02821b3be007f9d2af22b (patch) | |
| tree | 43bdcb0683971341f79f072504a40eea9b50368f /instrmem/v0.1/test.instr | |
| parent | deebf92127386873cb34d46f414d31c7a69adcfe (diff) | |
| download | cpu8_v-f3a300ce5927cad9ecf02821b3be007f9d2af22b.tar.gz cpu8_v-f3a300ce5927cad9ecf02821b3be007f9d2af22b.zip | |
Add instruction memory
Diffstat (limited to 'instrmem/v0.1/test.instr')
| -rw-r--r-- | instrmem/v0.1/test.instr | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/instrmem/v0.1/test.instr b/instrmem/v0.1/test.instr new file mode 100644 index 0000000..785176e --- /dev/null +++ b/instrmem/v0.1/test.instr @@ -0,0 +1,15 @@ +0000_0100_0000_0000 // load R0 <- Mem(R2 + 0) +0000_0100_0100_0001 // load R1 <- Mem(R2 + 1) +0010_0000_0101_0000 // Add R2 <- R0 + R1 +0001_0010_1000_0000 // Store Mem(R1 + 0) <- R2 +0011_0000_0101_0000 // sub R2 <- R0 - R1 +0100_0000_0101_0000 // invert R2 <- !R0 +0101_0000_0101_0000 // logical shift left R2 <- R0<<R1 +0110_0000_0101_0000 // logical shift right R2 <- R0>>R1 +0111_0000_0101_0000 // AND R2<- R0 AND R1 +1000_0000_0101_0000 // OR R2<- R0 OR R1 +1001_0000_0101_0000 // SLT R2 <- 1 if R0 < R1 +0010_0000_0000_0000 // Add R0 <- R0 + R0 +1011_0000_0100_0001 // BEQ branch to jump if R0=R1, PCnew= PC+2+offset<<1 = 28 => offset = 1 +1100_0000_0100_0000 // BNE branch to jump if R0!=R1, PCnew= PC+2+offset<<1 = 28 => offset = 0 +1101_0000_0000_0000 // J jump to the beginning address
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