5 files changed, 88 insertions, 0 deletions
diff --git a/instrmem/v0.1/Makefile b/instrmem/v0.1/Makefile
new file mode 100644
index 0000000..171b722
--- /dev/null
+++ b/instrmem/v0.1/Makefile
@@ -0,0 +1,9 @@
+make:
+	iverilog -g2005-sv -o instr_memory instr_memory.v
+	iverilog -g2005-sv  -o test_instr_memory instr_memory.v test_instr_memory.v
+
+test:
+	./test_instr_memory
+
+wave:
+	gtkwave test_instr_memory.vcd
+\ No newline at end of file
diff --git a/instrmem/v0.1/instr_memory.v b/instrmem/v0.1/instr_memory.v
new file mode 100644
index 0000000..943d358
--- /dev/null
+++ b/instrmem/v0.1/instr_memory.v
@@ -0,0 +1,18 @@
+`include "parameters.h"
+
+module instr_memory(
+    input [15:0]pc,
+    output [15:0]instruction
+);
+
+reg [`col - 1:0] memory [`row_i - 1:0];
+wire [3:0] rom_addr = pc[4:1];
+
+initial begin
+    $readmemb("test.instr",memory,0,14);
+end
+
+assign instruction = memory[rom_addr];
+
+endmodule
+
diff --git a/instrmem/v0.1/parameters.h b/instrmem/v0.1/parameters.h
new file mode 100644
index 0000000..4935dfc
--- /dev/null
+++ b/instrmem/v0.1/parameters.h
@@ -0,0 +1,13 @@
+`ifndef PARAMETERS_H_
+`define PARAMETERS_H_
+// fpga4student.com 
+// FPGA projects, VHDL projects, Verilog projects 
+// Verilog code for RISC Processor 
+// Parameter file
+`define col 16 // 16 bits instruction memory, data memory
+`define row_i 15 // instruction memory, instructions number, this number can be changed. Adding more instructions to verify your design is a good idea.
+`define row_d 8 // The number of data in data memory. We only use 8 data. Do not change this number. You can change the value of each data inside test.data file. Total number is fixed at 8. 
+`define filename "./test/50001111_50001212.o"
+`define simulation_time #160
+
+`endif
+\ No newline at end of file
diff --git a/instrmem/v0.1/test.instr b/instrmem/v0.1/test.instr
new file mode 100644
index 0000000..785176e
--- /dev/null
+++ b/instrmem/v0.1/test.instr
@@ -0,0 +1,15 @@
+0000_0100_0000_0000 // load R0 <- Mem(R2 + 0)
+0000_0100_0100_0001 // load R1 <- Mem(R2 + 1)
+0010_0000_0101_0000 // Add R2 <- R0 + R1
+0001_0010_1000_0000 // Store Mem(R1 + 0) <- R2
+0011_0000_0101_0000 // sub R2 <- R0 - R1
+0100_0000_0101_0000 // invert R2 <- !R0 
+0101_0000_0101_0000 // logical shift left R2 <- R0<<R1 
+0110_0000_0101_0000 // logical shift right R2 <- R0>>R1 
+0111_0000_0101_0000 // AND R2<- R0 AND R1 
+1000_0000_0101_0000 // OR R2<- R0 OR R1 
+1001_0000_0101_0000 // SLT R2 <- 1 if R0 < R1 
+0010_0000_0000_0000 // Add R0 <- R0 + R0
+1011_0000_0100_0001 // BEQ branch to jump if R0=R1, PCnew= PC+2+offset<<1 = 28 => offset = 1
+1100_0000_0100_0000 // BNE branch to jump if R0!=R1, PCnew= PC+2+offset<<1 = 28 => offset = 0
+1101_0000_0000_0000 // J jump to the beginning address
+\ No newline at end of file
diff --git a/instrmem/v0.1/test_instr_memory.v b/instrmem/v0.1/test_instr_memory.v
new file mode 100644
index 0000000..cc6f0b7
--- /dev/null
+++ b/instrmem/v0.1/test_instr_memory.v
@@ -0,0 +1,33 @@
+`timescale 1ns/1ps
+
+module test_instr_memory;
+
+reg [15:0]pc;
+reg [15:0]instruction;
+integer i;
+
+instr_memory uut(
+    .pc(pc),
+    .instruction(instruction)
+);
+
+initial begin 
+    $display("Start testing instruction memory");
+    $dumpfile("test_instr_memory.vcd");
+    $dumpvars(0,test_instr_memory);
+
+    for (i=0;i<=30;i=i+2)
+    begin
+        pc = i;
+        #10;
+    end
+
+end
+
+initial begin
+    $monitor("At time=%t",$time);
+end
+
+endmodule
+
+