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`timescale 1ns/1ps
module testbench_alu;
reg [7:0]var_1=0;
reg [7:0]var_2=0;
reg [3:0]op_sel;
reg carry;
//wire val;
//wire out;
wire [7:0]out;
//assign val=data;
alu uut (
.a(var_1),
.b(var_2),
.alu_sel(op_sel),
.alu_out(out),
.carry_out(carry)
);
initial begin
$display("addition");
$dumpfile("test_alu.vcd");
$dumpvars(0,testbench_alu);
var_1=0;
var_2=0;
op_sel=0;
#10 var_1=1;
var_2=0;
#10 var_1=0;
var_2=1;
#10 var_1=16;
var_2=16;
#10 var_1=64;
var_2=64;
$display("substraction");
$display("multiplication");
$display("division");
$display("logical shift left");
$display("logical shift right");
$display("rotate right");
$display("rotate left");
$display("and");
$display("or");
$display("xor");
$display("nor");
$display("nand");
$display("xnor");
$display("greater comparison");
$display("equal comparison");
end
initial begin
$monitor("At time %t d1=%h(%0d) d2=%h(%0d) op_sel=%0d out=%h(%0d)",$time,var_1,var_1,var_2,var_2,op_sel,out,out);
end
endmodule
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