alu/v0.1_16bit/alu.v


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module alu(
    input [15:0]a,b,
    input [2:0]alu_sel,
    output [15:0]alu_out,
    output carry_out
);

reg [7:0]alu_result;
wire [8:0]tmp;

assign alu_out=alu_result; //result from alu
//???
assign tmp = {1'b0,a}+{1'b0,b};


always @(*) 
begin
    case (alu_sel)
    4'b0000: //addition
        alu_result = a+b;
    4'b0001: //substraction
        alu_result = a-b;
    4'b0010: //multiplication
        alu_result = ~a;
    4'b0011: //division
        alu_result = a<<b;
    4'b0100: //logical shift left
        alu_result = a>>b;
    4'b0101: //logical shift right
        alu_result = a&b;
    4'b0110: //rotate right
        alu_result = a|b;
    4'b0111: //rotate left
        begin 
            if (a<b) alu_result = 16'd1;
            else alu_result = 16'd0;
        end
    default: 
        alu_result = a+b;
    endcase
end

assign zero = (alu_result==16'd0) ? 1'b1: 1'b0;


endmodule