and/v0.1/testbench.v


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`timescale 1ns/1ps

module testbench;

reg data_1=0;
reg data_2=0;
//reg [7:0]data2;

wire  val;
wire  out;
//wire  [7:0]out2;

//assign val=data;
and1 uut (
    .a(data_1),
    .b(data_2),
    .c(out)
);
/*
and8 uut1 (
    .a(data2),
    .b(out2)
);*/

initial begin
    $dumpfile("test_and.vcd");
    $dumpvars(0,testbench);
    data_1=0;
    data_2=0;
    #1 data_1=1;
    data_2=0;

    #10 data_1=0;
    data_2=1;

    #20 data_1=1;
    data_2=1;

    #30 data_1=0;
    data_2=0;

    #40;
end

initial begin
    $monitor("At time %t d1=%h(%0d) d2=%h(%0d) ",$time,data_1,data_1,data_2,data_2);
end 

endmodule