and/v0.1/testbench_and8.v


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`timescale 1ns/1ps

module testbench;

reg [7:0]data_1=0;
reg [7:0]data_2=0;
//reg [7:0]data2;

//wire  val;
//wire  out;
wire  [7:0]out;

//assign val=data;
and8 uut (
    .a(data_1),
    .b(data_2),
    .c(out)
);


initial begin
    $dumpfile("test_and8.vcd");
    $dumpvars(0,testbench);
    data_1=0;
    data_2=0;
    #10 data_1=1;
    data_2=0;

    #10 data_1=0;
    data_2=1;

    #10 data_1=1;
    data_2=1;

    #10 data_1=0;
    data_2=0;

    #10;
end

initial begin
    $monitor("At time %t d1=%h(%0d) d2=%h(%0d) ",$time,data_1,data_1,data_2,data_2);
end 

endmodule