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|
`timescale 1ns/1ps
module test_data_path;
reg clk;
reg jump;
reg mem_read;
reg mem_write;
reg alu_src;
reg reg_dst;
reg mem_to_reg;
reg reg_write;
reg bne;
reg beq;
reg [1:0]alu_op;
reg [3:0]opcode;
data_path uut(
.clk(clk),
.jump(jump),
.mem_read(mem_read),
.mem_write(mem_write),
.alu_src(alu_src),
.reg_dst(reg_dst),
.mem_to_reg(mem_to_reg),
.reg_write(reg_write),
.bne(bne),
.beq(beq),
.alu_op(alu_op),
.opcode(opcode)
);
initial begin
$display("Start testing data path");
$dumpfile("test_data_path.vcd");
$dumpvars(0,test_data_path);
clk=0;
jump=0;
mem_read=0;
mem_write=0;
alu_src=0;
reg_dst=0;
mem_to_reg=0;
reg_write=0;
bne=0;
beq=0;
alu_op=2'b00;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
#10
clk=1;
#10
clk=0;
end
initial begin
$monitor("At time=%t",$time);
end
endmodule
|
