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`timescale 1ns/1ps
module test_gpr_register;
reg clk;
reg reg_write_en;
reg [2:0]reg_write_dest;
reg [15:0]reg_write_data;
reg [2:0]reg_read_addr_1;
reg [15:0]reg_read_data_1;
reg [2:0]reg_read_addr_2;
reg [15:0]reg_read_data_2;
gpr_register gpr(
.clk(clk),
.reg_write_en(reg_write_en),
.reg_write_dest(reg_write_dest),
.reg_write_data(reg_write_data),
.reg_read_addr_1(reg_read_addr_1),
.reg_read_data_1(reg_read_data_1),
.reg_read_addr_2(reg_read_addr_2),
.reg_read_data_2(reg_read_data_2)
);
initial begin
$display("Start testing register");
$dumpfile("test_gpr_register.vcd");
$dumpvars(0,test_gpr_register);
clk=0;
reg_read_addr_1=0;
reg_read_addr_2=0;
reg_write_dest=0;
reg_write_en=0;
#10
clk=1;
reg_write_dest=1;
reg_write_data=16'hAA;
reg_write_en=1;
#10
clk=1;
#10
clk=0;
reg_write_dest=2;
reg_write_data=16'hBB;
reg_write_en=1;
#10
clk=1;
#10
clk=0;
reg_write_en=0;
reg_read_addr_1=0;
reg_read_addr_2=1;
//#10
//clk = 1;
//#10
//clk = 0;
#10
clk=1;
reg_read_addr_1=1;
reg_read_addr_2=2;
#10
clk = 0;
#10
clk = 1;
#10
clk = 0;
end
initial begin
$monitor("At time=%t",$time);
end
endmodule
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