risc_16bit_cpu/v0.1/test_risc_16bit_cpu.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

`include "parameters.h"

module test_risc_16bit_cpu;

// Inputs
reg clk;

// Instantiate the Unit Under Test (UUT)
risc_16bit_cpu uut (
    .clk(clk)
);

initial begin
    $display("Start testing risc 16bit cpu");
    $dumpfile("test_risc_16bit_cpu.vcd");
    $dumpvars(0,test_risc_16bit_cpu);


    clk <=0;
    `simulation_time;
    $finish;
end

always begin
        #5 clk = ~clk;
end

endmodule