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authordianshi <dianshi@main.lv>2022-01-05 21:03:04 +0000
committerdianshi <dianshi@main.lv>2022-01-05 21:03:04 +0000
commitb623b638fe1a0189416892415a1728839768539e (patch)
treeca71a74631f322dd4f1e407f7848a0395ade0a87 /alu/v0.1/alu.v
parent87d81f71cb794bbaf653098bfd88d0f59d7b20d5 (diff)
downloadcpu8_v-b623b638fe1a0189416892415a1728839768539e.tar.gz
cpu8_v-b623b638fe1a0189416892415a1728839768539e.zip
Added ALU
Diffstat (limited to 'alu/v0.1/alu.v')
-rw-r--r--alu/v0.1/alu.v57
1 files changed, 57 insertions, 0 deletions
diff --git a/alu/v0.1/alu.v b/alu/v0.1/alu.v
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+module alu(
+ input [7:0]a,b,
+ input [3:0]alu_sel,
+ output [7:0]alu_out,
+ output carry_out
+);
+
+reg [7:0]alu_result;
+wire [8:0]tmp;
+
+assign alu_out=alu_result; //result from alu
+//???
+assign tmp = {1'b0,a}+{1'b0,b};
+assign carry_out = tmp[8]; //carry out result
+
+always @(*)
+begin
+ case (alu_sel)
+ 4'b0000: //addition
+ alu_result = a+b;
+ 4'b0001: //substraction
+ alu_result = a-b;
+ 4'b0010: //multiplication
+ alu_result = a*b;
+ 4'b0011: //division
+ alu_result = a/b;
+ 4'b0100: //logical shift left
+ alu_result = a<<1;
+ 4'b0101: //logical shift right
+ alu_result = a>>1;
+ 4'b0110: //rotate right
+ alu_result = {a[6:0],a[7]};
+ 4'b0111: //rotate left
+ alu_result = {a[0],a[7:1]};
+ 4'b1000: //and
+ alu_result = a&b;
+ 4'b1001: //or
+ alu_result = a|b;
+ 4'b1010: //xor
+ alu_result = a^b;
+ 4'b1011: //nor
+ alu_result = ~(a|b);
+ 4'b1100: //nand
+ alu_result = ~(a&b);
+ 4'b1101: //xnor
+ alu_result = ~(a^b);
+ 4'b1110: //greate comparison
+ alu_result = (a>b)?8'b1:8'b0;
+ 4'b1111:
+ alu_result = (a==b)?8'b1:8'b0;
+ default:
+ alu_result = a+b;
+ endcase
+end
+
+
+endmodule \ No newline at end of file