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authordianshi <dianshi@main.lv>2022-01-05 20:54:13 +0000
committerdianshi <dianshi@main.lv>2022-01-05 20:54:13 +0000
commit87d81f71cb794bbaf653098bfd88d0f59d7b20d5 (patch)
tree1ebe5aa6567bc345a19d8fc092f1613b6f62639d /and/v0.1/Makefile
downloadcpu8_v-87d81f71cb794bbaf653098bfd88d0f59d7b20d5.tar.gz
cpu8_v-87d81f71cb794bbaf653098bfd88d0f59d7b20d5.zip
Added and8
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diff --git a/and/v0.1/Makefile b/and/v0.1/Makefile
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+make:
+ iverilog -g2005-sv -o and and.v
+ iverilog -g2005-sv -o and8 and8.v
+ iverilog -g2005-sv -o alu alu.v
+ iverilog -g2005-sv -o test_and testbench.v and.v and8.v
+ iverilog -g2005-sv -o test_and8 testbench_and8.v and8.v
+ iverilog -g2005-sv -o test_alu testbench_alu.v alu.v
+
+test:
+ vvp test_and
+
+test_and8:
+ vvp test_and8
+
+test_alu:
+ vvp test_alu
+
+wave:
+ gtkwave test_and.vcd \ No newline at end of file