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-rw-r--r--and/v0.1/Makefile19
-rw-r--r--and/v0.1/and.v9
-rw-r--r--and/v0.1/and8.v9
-rw-r--r--and/v0.1/testbench.v49
-rw-r--r--and/v0.1/testbench_and8.v45
5 files changed, 131 insertions, 0 deletions
diff --git a/and/v0.1/Makefile b/and/v0.1/Makefile
new file mode 100644
index 0000000..e0cdfbb
--- /dev/null
+++ b/and/v0.1/Makefile
@@ -0,0 +1,19 @@
+make:
+ iverilog -g2005-sv -o and and.v
+ iverilog -g2005-sv -o and8 and8.v
+ iverilog -g2005-sv -o alu alu.v
+ iverilog -g2005-sv -o test_and testbench.v and.v and8.v
+ iverilog -g2005-sv -o test_and8 testbench_and8.v and8.v
+ iverilog -g2005-sv -o test_alu testbench_alu.v alu.v
+
+test:
+ vvp test_and
+
+test_and8:
+ vvp test_and8
+
+test_alu:
+ vvp test_alu
+
+wave:
+ gtkwave test_and.vcd \ No newline at end of file
diff --git a/and/v0.1/and.v b/and/v0.1/and.v
new file mode 100644
index 0000000..a75b926
--- /dev/null
+++ b/and/v0.1/and.v
@@ -0,0 +1,9 @@
+module and1(
+ input a,
+ input b,
+ output c
+);
+
+ assign c = b&a;
+
+endmodule \ No newline at end of file
diff --git a/and/v0.1/and8.v b/and/v0.1/and8.v
new file mode 100644
index 0000000..40cc298
--- /dev/null
+++ b/and/v0.1/and8.v
@@ -0,0 +1,9 @@
+module and8(
+ input [7:0]a,
+ input [7:0]b,
+ output [7:0]c
+);
+
+ assign c = b&a;
+
+endmodule \ No newline at end of file
diff --git a/and/v0.1/testbench.v b/and/v0.1/testbench.v
new file mode 100644
index 0000000..1832e60
--- /dev/null
+++ b/and/v0.1/testbench.v
@@ -0,0 +1,49 @@
+`timescale 1ns/1ps
+
+module testbench;
+
+reg data_1=0;
+reg data_2=0;
+//reg [7:0]data2;
+
+wire val;
+wire out;
+//wire [7:0]out2;
+
+//assign val=data;
+and1 uut (
+ .a(data_1),
+ .b(data_2),
+ .c(out)
+);
+/*
+and8 uut1 (
+ .a(data2),
+ .b(out2)
+);*/
+
+initial begin
+ $dumpfile("test_and.vcd");
+ $dumpvars(0,testbench);
+ data_1=0;
+ data_2=0;
+ #1 data_1=1;
+ data_2=0;
+
+ #10 data_1=0;
+ data_2=1;
+
+ #20 data_1=1;
+ data_2=1;
+
+ #30 data_1=0;
+ data_2=0;
+
+ #40;
+end
+
+initial begin
+ $monitor("At time %t d1=%h(%0d) d2=%h(%0d) ",$time,data_1,data_1,data_2,data_2);
+end
+
+endmodule \ No newline at end of file
diff --git a/and/v0.1/testbench_and8.v b/and/v0.1/testbench_and8.v
new file mode 100644
index 0000000..e5efc71
--- /dev/null
+++ b/and/v0.1/testbench_and8.v
@@ -0,0 +1,45 @@
+`timescale 1ns/1ps
+
+module testbench;
+
+reg [7:0]data_1=0;
+reg [7:0]data_2=0;
+//reg [7:0]data2;
+
+//wire val;
+//wire out;
+wire [7:0]out;
+
+//assign val=data;
+and8 uut (
+ .a(data_1),
+ .b(data_2),
+ .c(out)
+);
+
+
+initial begin
+ $dumpfile("test_and8.vcd");
+ $dumpvars(0,testbench);
+ data_1=0;
+ data_2=0;
+ #10 data_1=1;
+ data_2=0;
+
+ #10 data_1=0;
+ data_2=1;
+
+ #10 data_1=1;
+ data_2=1;
+
+ #10 data_1=0;
+ data_2=0;
+
+ #10;
+end
+
+initial begin
+ $monitor("At time %t d1=%h(%0d) d2=%h(%0d) ",$time,data_1,data_1,data_2,data_2);
+end
+
+endmodule \ No newline at end of file