summaryrefslogtreecommitdiff
path: root/datamem/v0.1/parameters.h
diff options
context:
space:
mode:
authordianshi <dianshi@main.lv>2022-01-13 21:41:49 +0000
committerdianshi <dianshi@main.lv>2022-01-13 21:41:49 +0000
commitdeebf92127386873cb34d46f414d31c7a69adcfe (patch)
tree040b7dfbb27c4a47b18956d7b0d205a8cc659c62 /datamem/v0.1/parameters.h
parent37bd6ad2b012754fc3573f3c2529444ce8d75f36 (diff)
downloadcpu8_v-deebf92127386873cb34d46f414d31c7a69adcfe.tar.gz
cpu8_v-deebf92127386873cb34d46f414d31c7a69adcfe.zip
Added datamem with 8bytes of memory
Diffstat (limited to 'datamem/v0.1/parameters.h')
-rw-r--r--datamem/v0.1/parameters.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/datamem/v0.1/parameters.h b/datamem/v0.1/parameters.h
new file mode 100644
index 0000000..4935dfc
--- /dev/null
+++ b/datamem/v0.1/parameters.h
@@ -0,0 +1,13 @@
+`ifndef PARAMETERS_H_
+`define PARAMETERS_H_
+// fpga4student.com
+// FPGA projects, VHDL projects, Verilog projects
+// Verilog code for RISC Processor
+// Parameter file
+`define col 16 // 16 bits instruction memory, data memory
+`define row_i 15 // instruction memory, instructions number, this number can be changed. Adding more instructions to verify your design is a good idea.
+`define row_d 8 // The number of data in data memory. We only use 8 data. Do not change this number. You can change the value of each data inside test.data file. Total number is fixed at 8.
+`define filename "./test/50001111_50001212.o"
+`define simulation_time #160
+
+`endif \ No newline at end of file