Added datamem with 8bytes of memory

4 files changed, 146 insertions, 0 deletions

diff --git a/datamem/v0.1/Makefile b/datamem/v0.1/Makefile
new file mode 100644
index 0000000..871c36d
--- /dev/null
+++ b/datamem/v0.1/Makefile
@@ -0,0 +1,9 @@
+make:
+	iverilog -g2005-sv -o data_memory data_memory.v
+	iverilog -g2005-sv  -o test_data_memory data_memory.v test_data_memory.v
+
+test:
+	./test_data_memory
+
+wave:
+	gtkwave test_data_memory.vcd
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diff --git a/datamem/v0.1/data_memory.v b/datamem/v0.1/data_memory.v
new file mode 100644
index 0000000..bf29390
--- /dev/null
+++ b/datamem/v0.1/data_memory.v
@@ -0,0 +1,49 @@
+`include "parameters.h"
+
+module data_memory(
+    input clk,
+    input [15:0]mem_access_addr, //address input
+    input [15:0]mem_write_data,  //data to be written
+    input mem_write_en,   
+    input mem_read,
+    output [15:0] mem_read_data  //read data
+);
+
+//amount of memory
+reg [`col-1:0]memory[`row_d-1:0];
+integer f;
+wire [2:0]ram_addr=mem_access_addr[2:0];
+
+//load data to memory
+initial begin 
+    $readmemb("test.data",memory);
+    f = $fopen(`filename);
+    $monitor(f,"time=%d\n",$time,
+        "\tmemory[0] = %b\n", memory[0],   
+        "\tmemory[1] = %b\n", memory[1],
+        "\tmemory[2] = %b\n", memory[2],
+        "\tmemory[3] = %b\n", memory[3],
+        "\tmemory[4] = %b\n", memory[4],
+        "\tmemory[5] = %b\n", memory[5],
+        "\tmemory[6] = %b\n", memory[6],
+        "\tmemory[7] = %b\n", memory[7]
+    );
+    `simulation_time;
+    $fclose(f);
+end
+
+//if memory write is enable write to memory
+always @(posedge clk) begin
+    if (mem_write_en)
+        memory[ram_addr] <= mem_write_data;
+end
+
+
+
+
+//if memory read is enabled then read memory otherwise output zeros
+assign mem_read_data = (mem_read==1'b1) ? memory[ram_addr]: 16'd0;
+
+
+endmodule
+
diff --git a/datamem/v0.1/parameters.h b/datamem/v0.1/parameters.h
new file mode 100644
index 0000000..4935dfc
--- /dev/null
+++ b/datamem/v0.1/parameters.h
@@ -0,0 +1,13 @@
+`ifndef PARAMETERS_H_
+`define PARAMETERS_H_
+// fpga4student.com 
+// FPGA projects, VHDL projects, Verilog projects 
+// Verilog code for RISC Processor 
+// Parameter file
+`define col 16 // 16 bits instruction memory, data memory
+`define row_i 15 // instruction memory, instructions number, this number can be changed. Adding more instructions to verify your design is a good idea.
+`define row_d 8 // The number of data in data memory. We only use 8 data. Do not change this number. You can change the value of each data inside test.data file. Total number is fixed at 8. 
+`define filename "./test/50001111_50001212.o"
+`define simulation_time #160
+
+`endif
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diff --git a/datamem/v0.1/test_data_memory.v b/datamem/v0.1/test_data_memory.v
new file mode 100644
index 0000000..e0633c1
--- /dev/null
+++ b/datamem/v0.1/test_data_memory.v
@@ -0,0 +1,75 @@
+`timescale 1ns/1ps
+
+module test_data_memory;
+
+reg clk;
+reg [15:0]mem_access_addr;
+reg [15:0]mem_write_data;
+reg mem_write_en;
+reg mem_read;
+reg [15:0]mem_read_data;
+
+data_memory uut (
+    .clk(clk),
+    .mem_access_addr(mem_access_addr),
+    .mem_write_data(mem_write_data),
+    .mem_write_en(mem_write_en),
+    .mem_read(mem_read),
+    .mem_read_data(mem_read_data)
+);
+
+initial begin 
+    $display("Start testing data memory");
+    $dumpfile("test_data_memory.vcd");
+    $dumpvars(0,test_data_memory);
+
+    clk=0;
+    mem_write_en = 0;
+    mem_access_addr = 0;
+    mem_read = 0;
+
+    #10 clk=0;
+    mem_write_en = 0;
+    mem_access_addr = 0;
+    mem_read = 0;
+
+    #10 clk=1;
+    mem_access_addr = 1;
+    mem_read = 1;
+
+    #10 clk=0;
+    mem_access_addr = 2;
+    mem_read = 1;
+
+    #10 clk=1;
+     mem_access_addr = 3;
+
+    #10 clk=0;
+    mem_access_addr = 4;
+
+    #10 clk=1;
+    mem_access_addr = 4;
+    mem_read=0;
+
+    #10 clk=0;
+    mem_write_en=1;
+    mem_write_data=8'hAA;
+
+    #10 clk=1;
+    
+    mem_read=0;
+
+    #10 clk=0;
+    mem_write_en=0;
+    mem_read=1;
+
+
+    #10 clk=1;
+end
+
+
+initial begin
+    $monitor("At time=%t",$time);
+end
+
+endmodule
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