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| author | dianshi <dianshi@main.lv> | 2022-01-05 21:13:45 +0000 |
|---|---|---|
| committer | dianshi <dianshi@main.lv> | 2022-01-05 21:13:45 +0000 |
| commit | 37bd6ad2b012754fc3573f3c2529444ce8d75f36 (patch) | |
| tree | 865a15e80b0ef3b4e69cd62249ba631832bc706c | |
| parent | b623b638fe1a0189416892415a1728839768539e (diff) | |
| download | cpu8_v-37bd6ad2b012754fc3573f3c2529444ce8d75f36.tar.gz cpu8_v-37bd6ad2b012754fc3573f3c2529444ce8d75f36.zip | |
Update AND model
| -rw-r--r-- | and/v0.1/Makefile | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/and/v0.1/Makefile b/and/v0.1/Makefile index e0cdfbb..c34888f 100644 --- a/and/v0.1/Makefile +++ b/and/v0.1/Makefile @@ -1,19 +1,13 @@ make: iverilog -g2005-sv -o and and.v iverilog -g2005-sv -o and8 and8.v - iverilog -g2005-sv -o alu alu.v iverilog -g2005-sv -o test_and testbench.v and.v and8.v iverilog -g2005-sv -o test_and8 testbench_and8.v and8.v - iverilog -g2005-sv -o test_alu testbench_alu.v alu.v - test: - vvp test_and - -test_and8: vvp test_and8 -test_alu: - vvp test_alu +test_and: + vvp test_and wave: - gtkwave test_and.vcd
\ No newline at end of file + gtkwave test_and8.vcd |