diff options
author | dianshi <dianshi@main.lv> | 2022-01-19 22:03:50 +0000 |
---|---|---|
committer | dianshi <dianshi@main.lv> | 2022-01-19 22:03:50 +0000 |
commit | 8661ed2084e8d50ef19a2827484fefd07c4f20e1 (patch) | |
tree | 8a516be79571d1ef46ecabe676ffa7ce17c6ffab /gpr/v0.1/gpr_register.v | |
parent | f3a300ce5927cad9ecf02821b3be007f9d2af22b (diff) | |
download | cpu8_v-8661ed2084e8d50ef19a2827484fefd07c4f20e1.tar.gz cpu8_v-8661ed2084e8d50ef19a2827484fefd07c4f20e1.zip |
Added general purpose memory
Diffstat (limited to 'gpr/v0.1/gpr_register.v')
-rw-r--r-- | gpr/v0.1/gpr_register.v | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/gpr/v0.1/gpr_register.v b/gpr/v0.1/gpr_register.v new file mode 100644 index 0000000..7f27be9 --- /dev/null +++ b/gpr/v0.1/gpr_register.v @@ -0,0 +1,36 @@ +module gpr_register( + input clk, + + input reg_write_en, + input [2:0]reg_write_dest, + input [15:0]reg_write_data, + + input [2:0]reg_read_addr_1, + output [15:0]reg_read_data_1, + + input [2:0]reg_read_addr_2, + output [15:0]reg_read_data_2 +); + +reg [15:0] reg_array[7:0]; +integer i; + +//set initial values of registers to 0 +initial begin + for (i=0; i<8; i=i+1) + reg_array[i] <= 16'd0; +end + +//handlr write behaviour +always @(posedge clk) begin + if (reg_write_en) begin + reg_array[reg_write_dest] = reg_write_data; + end +end + +assign reg_read_data_1 = reg_array[reg_read_addr_1]; +//assign reg_read_data_1 = reg_array[3'b001]; +assign reg_read_data_2 = reg_array[reg_read_addr_2]; + + +endmodule
\ No newline at end of file |