3 files changed, 134 insertions, 0 deletions
diff --git a/gpr/v0.1/Makefile b/gpr/v0.1/Makefile
new file mode 100644
index 0000000..9cd2a23
--- /dev/null
+++ b/gpr/v0.1/Makefile
@@ -0,0 +1,9 @@
+make:
+	iverilog -g2005-sv -o gpr_register gpr_register.v
+	iverilog -g2005-sv  -o test_gpr_register gpr_register.v test_gpr_register.v
+
+test:
+	./test_gpr_register
+
+wave:
+	gtkwave test_gpr_register.vcd
+\ No newline at end of file
diff --git a/gpr/v0.1/gpr_register.v b/gpr/v0.1/gpr_register.v
new file mode 100644
index 0000000..7f27be9
--- /dev/null
+++ b/gpr/v0.1/gpr_register.v
@@ -0,0 +1,36 @@
+module gpr_register(
+    input clk,
+    
+    input reg_write_en,
+    input [2:0]reg_write_dest,
+    input [15:0]reg_write_data,
+    
+    input [2:0]reg_read_addr_1,
+    output [15:0]reg_read_data_1,
+
+    input [2:0]reg_read_addr_2,
+    output [15:0]reg_read_data_2
+);
+
+reg [15:0] reg_array[7:0];
+integer i;
+
+//set initial values of registers to 0
+initial begin
+    for (i=0; i<8; i=i+1)
+        reg_array[i] <= 16'd0; 
+end
+
+//handlr write behaviour
+always @(posedge clk) begin
+    if (reg_write_en) begin
+        reg_array[reg_write_dest] = reg_write_data;
+    end
+end
+
+assign reg_read_data_1 = reg_array[reg_read_addr_1];
+//assign reg_read_data_1 = reg_array[3'b001];
+assign reg_read_data_2 = reg_array[reg_read_addr_2];
+
+
+endmodule
+\ No newline at end of file
diff --git a/gpr/v0.1/test_gpr_register.v b/gpr/v0.1/test_gpr_register.v
new file mode 100644
index 0000000..bad146b
--- /dev/null
+++ b/gpr/v0.1/test_gpr_register.v
@@ -0,0 +1,89 @@
+`timescale 1ns/1ps
+
+module test_gpr_register;
+
+    reg clk;
+    
+    reg reg_write_en;
+    reg [2:0]reg_write_dest;
+    reg [15:0]reg_write_data;
+    
+    reg [2:0]reg_read_addr_1;
+    reg [15:0]reg_read_data_1;
+
+    reg [2:0]reg_read_addr_2;
+    reg [15:0]reg_read_data_2;
+
+
+gpr_register gpr(
+    .clk(clk),
+    .reg_write_en(reg_write_en),
+    .reg_write_dest(reg_write_dest),
+    .reg_write_data(reg_write_data),
+    .reg_read_addr_1(reg_read_addr_1),
+    .reg_read_data_1(reg_read_data_1),
+    .reg_read_addr_2(reg_read_addr_2),
+    .reg_read_data_2(reg_read_data_2)
+);
+initial begin 
+    $display("Start testing register");
+    $dumpfile("test_gpr_register.vcd");
+    $dumpvars(0,test_gpr_register);
+
+    clk=0;
+    reg_read_addr_1=0;
+    reg_read_addr_2=0;
+    reg_write_dest=0;
+    reg_write_en=0;
+
+    #10
+    clk=1;
+    reg_write_dest=1;
+    reg_write_data=16'hAA;
+    reg_write_en=1;
+
+    #10
+    clk=1;
+
+    #10
+    clk=0;
+    reg_write_dest=2;
+    reg_write_data=16'hBB;
+    reg_write_en=1;
+
+    #10
+    clk=1;
+
+    #10 
+    clk=0;
+    reg_write_en=0;
+    reg_read_addr_1=0;
+    reg_read_addr_2=1;
+
+    //#10
+    //clk = 1;
+    
+    //#10
+    //clk = 0;
+
+    #10
+    clk=1;
+    reg_read_addr_1=1;
+    reg_read_addr_2=2;
+
+    #10
+    clk = 0;
+
+    #10
+    clk = 1;
+
+    #10
+    clk = 0;
+
+end
+
+initial begin
+    $monitor("At time=%t",$time);
+end
+
+endmodule
+\ No newline at end of file