Add running risc 16bit cpu v0.1

3 files changed, 36 insertions, 20 deletions

diff --git a/risc_16bit_cpu/v0.1/Makefile b/risc_16bit_cpu/v0.1/Makefile
index 5d6accc..fd41e8f 100644
--- a/risc_16bit_cpu/v0.1/Makefile
+++ b/risc_16bit_cpu/v0.1/Makefile
@@ -1,26 +1,18 @@
+
+I_INSTRMEM=-I../../instrmem/v0.1 ../../instrmem/v0.1/instr_memory.v
+I_GPR=-I../../gpr/v0.1 ../../gpr/v0.1/gpr_register.v
+I_ALUCONTROL=-I../../alu_control/v0.1 ../../alu_control/v0.1/alu_control.v 
+I_ALU8=-I../../alu/v0.1_16bit ../../alu/v0.1_16bit/alu.v
+I_DATAMEM=-I../../datamem/v0.1 ../../datamem/v0.1/data_memory.v
+I_CONTROLUNIT=-I../../control_unit/v0.1 ../../control_unit/v0.1/control_unit.v
+I_DATAPATH=-I../../datapath/v0.1 ../../datapath/v0.1/data_path.v
+
 make:
-	iverilog -g2005-sv -o alu_8 alu_8.v
-	iverilog -g2005-sv -o data_memory data_memory.v
-	iverilog -g2005-sv -o instr_memory instr_memory.v
-	iverilog -g2005-sv -o gpr_register gpr_register.v
-	iverilog -g2005-sv -o alu_control alu_control.v
-	iverilog -g2005-sv -o data_path data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v
-	iverilog -g2005-sv -o control_unit control_unit.v
-	iverilog -g2005-sv -o risc_16bit_cpu risc_16bit_cpu.v control_unit.v data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v
-	iverilog -g2005-sv -o test_data_memory data_memory.v test_data_memory.v
-	iverilog -g2005-sv -o test_instr_memory instr_memory.v test_instr_memory.v
-	iverilog -g2005-sv -o test_gpr_register gpr_register.v test_gpr_register.v
-	iverilog -g2005-sv -o test_alu_control alu_control.v test_alu_control.v
-	iverilog -g2005-sv -o test_data_path data_path.v test_data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v
-	iverilog -g2005-sv -o test_risc_16bit_cpu test_risc_16bit_cpu.v risc_16bit_cpu.v control_unit.v data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v
+	iverilog -g2005-sv -o risc_16bit_cpu risc_16bit_cpu.v $(I_INSTRMEM) $(I_GPR) $(I_ALUCONTROL) $(I_ALU8) $(I_DATAMEM) $(I_CONTROLUNIT) $(I_DATAPATH)
+	iverilog -g2005-sv -o test_risc_16bit_cpu test_risc_16bit_cpu.v risc_16bit_cpu.v $(I_INSTRMEM) $(I_GPR) $(I_ALUCONTROL) $(I_ALU8) $(I_DATAMEM) $(I_CONTROLUNIT) $(I_DATAPATH)
 
 test:
-	./test_data_memory
-	./test_instr_memory
-	./test_gpr_register
-	./test_alu_control
-	./test_data_path
 	./test_risc_16bit_cpu
 
 wave:
-	gtkwave test_data_path.vcd
\ No newline at end of file
+	gtkwave test_risc_16bit_cpu.vcd
\ No newline at end of file
diff --git a/risc_16bit_cpu/v0.1/test.data b/risc_16bit_cpu/v0.1/test.data
new file mode 100644
index 0000000..65f7a06
--- /dev/null
+++ b/risc_16bit_cpu/v0.1/test.data
@@ -0,0 +1,8 @@
+0000_0000_0000_0001
+0000_0000_0000_0010
+0000_0000_0000_1001
+0000_0000_0000_1010
+0000_0000_1000_0001
+0000_0000_1000_0010
+0000_0000_0000_0001
+0000_0000_0000_0010
\ No newline at end of file
diff --git a/risc_16bit_cpu/v0.1/test.instr b/risc_16bit_cpu/v0.1/test.instr
new file mode 100644
index 0000000..ef81860
--- /dev/null
+++ b/risc_16bit_cpu/v0.1/test.instr
@@ -0,0 +1,16 @@
+0000_0100_0000_0000 // load R0 <- Mem(R2 + 0)
+0000_0100_0100_0001 // load R1 <- Mem(R2 + 1)
+0010_0000_0101_0000 // Add R2 <- R0 + R1
+0001_0010_1000_0000 // Store Mem(R1 + 0) <- R2
+0011_0000_0101_0000 // sub R2 <- R0 - R1
+0100_0000_0101_0000 // invert R2 <- !R0 
+0101_0000_0101_0000 // logical shift left R2 <- R0<<R1 
+0110_0000_0101_0000 // logical shift right R2 <- R0>>R1 
+0111_0000_0101_0000 // AND R2<- R0 AND R1 
+1000_0000_0101_0000 // OR R2<- R0 OR R1 
+1001_0000_0101_0000 // SLT R2 <- 1 if R0 < R1 
+0010_0000_0000_0000 // Add R0 <- R0 + R0
+1011_0000_0100_0001 // BEQ branch to jump if R0=R1, PCnew= PC+2+offset<<1 = 28 => offset = 1
+1100_0000_0100_0000 // BNE branch to jump if R0!=R1, PCnew= PC+2+offset<<1 = 28 => offset = 0
+1101_0000_0000_0000 // J jump to the beginning address
+0000_0100_0000_0000
\ No newline at end of file