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authordianshi <dianshi@main.lv>2022-02-14 07:48:24 +0000
committerdianshi <dianshi@main.lv>2022-02-14 07:48:24 +0000
commitf52f1af38851b784862175ff2806bda622b0ec47 (patch)
treeb867a56d42f4006b171bbd547aafaaa6d736d101 /risc_16bit_cpu/v0.1/Makefile
parent2a54718dc842d1be84d1470827b538bdaab2cb28 (diff)
downloadcpu8_v-f52f1af38851b784862175ff2806bda622b0ec47.tar.gz
cpu8_v-f52f1af38851b784862175ff2806bda622b0ec47.zip
Add datapatch v0.1
Diffstat (limited to 'risc_16bit_cpu/v0.1/Makefile')
-rw-r--r--risc_16bit_cpu/v0.1/Makefile26
1 files changed, 26 insertions, 0 deletions
diff --git a/risc_16bit_cpu/v0.1/Makefile b/risc_16bit_cpu/v0.1/Makefile
new file mode 100644
index 0000000..5d6accc
--- /dev/null
+++ b/risc_16bit_cpu/v0.1/Makefile
@@ -0,0 +1,26 @@
+make:
+ iverilog -g2005-sv -o alu_8 alu_8.v
+ iverilog -g2005-sv -o data_memory data_memory.v
+ iverilog -g2005-sv -o instr_memory instr_memory.v
+ iverilog -g2005-sv -o gpr_register gpr_register.v
+ iverilog -g2005-sv -o alu_control alu_control.v
+ iverilog -g2005-sv -o data_path data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v
+ iverilog -g2005-sv -o control_unit control_unit.v
+ iverilog -g2005-sv -o risc_16bit_cpu risc_16bit_cpu.v control_unit.v data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v
+ iverilog -g2005-sv -o test_data_memory data_memory.v test_data_memory.v
+ iverilog -g2005-sv -o test_instr_memory instr_memory.v test_instr_memory.v
+ iverilog -g2005-sv -o test_gpr_register gpr_register.v test_gpr_register.v
+ iverilog -g2005-sv -o test_alu_control alu_control.v test_alu_control.v
+ iverilog -g2005-sv -o test_data_path data_path.v test_data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v
+ iverilog -g2005-sv -o test_risc_16bit_cpu test_risc_16bit_cpu.v risc_16bit_cpu.v control_unit.v data_path.v instr_memory.v gpr_register.v alu_control.v alu_8.v data_memory.v
+
+test:
+ ./test_data_memory
+ ./test_instr_memory
+ ./test_gpr_register
+ ./test_alu_control
+ ./test_data_path
+ ./test_risc_16bit_cpu
+
+wave:
+ gtkwave test_data_path.vcd \ No newline at end of file